chisel
7.9.0+2-5294dafe-SNAPSHOT
API
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chisel/svsim/CommonCompilationSettings/VerilogPreprocessorDefine

VerilogPreprocessorDefine

svsim.CommonCompilationSettings.VerilogPreprocessorDefine
See theVerilogPreprocessorDefine companion class
object VerilogPreprocessorDefine

Attributes

Companion
class
Source
Backend.scala
Graph
Supertypes
trait Product
trait Mirror
class Object
trait Matchable
class Any
Self type

Members list

Type members

Inherited and Abstract types

type MirroredElemLabels <: Tuple

The names of the product elements

The names of the product elements

Attributes

Inherited from:
Mirror
Source
Mirror.scala
type MirroredLabel <: String

The name of the type

The name of the type

Attributes

Inherited from:
Mirror
Source
Mirror.scala

Value members

Concrete methods

def apply(name: String, value: String): VerilogPreprocessorDefine

Attributes

Source
Backend.scala
def apply(name: String): VerilogPreprocessorDefine

Attributes

Source
Backend.scala
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