DesignAnnotation

chisel3.stage.DesignAnnotation
case class DesignAnnotation[DUT <: RawModule](design: DUT, layers: Seq[Layer] = ...) extends NoTargetAnnotation, Unserializable

Contains the top-level elaborated Chisel design.

By default is created during Chisel elaboration and passed to the FIRRTL compiler.

Type parameters

DUT

Type of the top-level Chisel design

Value parameters

design

top-level Chisel design

Attributes

Source
ChiselAnnotations.scala
Graph
Supertypes
trait Serializable
trait Annotation
trait Product
trait Equals
class Object
trait Matchable
class Any
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Members list

Value members

Inherited methods

def productElementNames: Iterator[String]

Attributes

Inherited from:
Product
def productIterator: Iterator[Any]

Attributes

Inherited from:
Product
def serialize: String

Optional pretty print

Optional pretty print

Attributes

Note

rarely used

Inherited from:
Annotation
Source
Annotation.scala
def update(renames: RenameMap): Seq[NoTargetAnnotation]

Update the target based on how signals are renamed

Update the target based on how signals are renamed

Attributes

Inherited from:
NoTargetAnnotation
Source
Annotation.scala