chiseltest

ChiselTest Compatibility Layer for Chisel 7

This package provides a drop-in replacement for the ChiselTest library that was removed in Chisel 7. It preserves the familiar ChiselTest API while delegating to Chisel 7's ChiselSim underneath.

Usage:

import chiseltest._
import org.scalatest.flatspec.AnyFlatSpec

class MyTest extends AnyFlatSpec with ChiselScalatestTester {
 it should "work" in {
   test(new MyModule) { dut =>
     dut.io.in.poke(42.U)
     dut.clock.step()
     dut.io.out.expect(42.U)
   }
 }
}

Key Components:

testableData, testableUInt, testableBoolExt: Implicit conversions for poke/peek/expect
testableClock: Clock stepping and control
DecoupledIOOps: Utilities for Decoupled interface testing
ChiselScalatestTester: ScalaTest integration trait

See README.md for detailed documentation.

Attributes

Members list

Packages

Formal compatibility API placeholders.

Formal verification is currently unsupported in this compatibility layer. Any usage should fail at compile time to avoid vacuously passing tests.

Attributes

Type members

Classlikes

ChiselTest-compatible API that delegates to ChiselSim (Chisel 7)

This trait provides the ChiselTest API that users are familiar with from Chisel 6, but internally uses ChiselSim from Chisel 7 to perform the actual testing.

VCD GENERATION SUPPORT: This compatibility layer supports VCD generation when WriteVcdAnnotation is used. VCD files are generated in: build/chiselsim/ /workdir-verilator/trace.vcd

AUTOMATIC RESET FEATURE: By default, this trait automatically resets the module before running tests, mimicking ChiselTest's behavior from Chisel 6.

To disable auto-reset or customize the reset duration:

class MyTest extends AnyFlatSpec with ChiselScalatestTester {
 override def autoResetEnabled: Boolean = false  // Disable auto-reset
 override def resetCycles: Int = 5               // Or change duration
}

Example usage with VCD:

import chiseltest._
import org.scalatest.flatspec.AnyFlatSpec

class MyModuleSpec extends AnyFlatSpec with ChiselScalatestTester {
 behavior of "MyModule"

 it should "generate waveforms" in {
   test(new MyModule).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
     dut.io.in.poke(42.U)
     dut.clock.step()
     dut.io.out.expect(42.U)
   }
   // VCD file: build/chiselsim/<timestamp>/workdir-verilator/trace.vcd
 }
}

Attributes

Source: ChiselScalatestTester.scala
Supertypes: class Object

trait Matchable

class Any

Compatibility placeholder for ChiselTest's DecoupledDriver class.

Decoupled enqueue/dequeue helpers are provided via implicit extensions in package object chiseltest. Use import chiseltest._ to access:

enqueueNow, enqueueSeq
expectDequeueNow, expectDequeueSeq
initSource, initSink

Attributes

Source: DecoupledDriver.scala
Supertypes: class Object

trait Matchable

class Any

Attributes

Source: package.scala
Supertypes: class AnyVal

trait Matchable

class Any

Attributes

Source: package.scala
Supertypes: class Object

trait Matchable

class Any

Attributes

Source: package.scala
Supertypes: trait Singleton

trait Product

trait Mirror

trait Serializable

trait Product

trait Equals

class Object

trait Matchable

class Any
Show all
Self type: VerilatorBackendAnnotation.type

Attributes

Source: package.scala
Supertypes: trait Singleton

trait Product

trait Mirror

trait Serializable

trait Product

trait Equals

class Object

trait Matchable

class Any
Show all
Self type: WriteVcdAnnotation.type