The util that records the reference map from original Data/Module annotated in Chisel and final FIRRTL.
Attributes
Example
class Dut extends Module {
val a = WireDefault(Bool())
Trace.traceName(a)
}
val annos = (new ChiselStage).execute(Seq(ChiselGeneratorAnnotation(() => new Dut)))
val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[CollideModule]
// get final reference of `a` Seq(ReferenceTarget("Dut", "Dut", Seq.empty, "a", Seq.empty))
val firrtlReferenceOfDutA = finalTarget(annos)(dut.a)