chisel
7.9.0+2-5294dafe-SNAPSHOT
API
Generated with
chisel/chisel3

chisel3

package chisel3

This package contains the main chisel3 API.

Attributes

Members list

Packages

package chisel3.choice

This package contains Chisel language definitions for describing configuration options and their accepted values.

This package contains Chisel language definitions for describing configuration options and their accepted values.

Attributes

package chisel3.connectable
package chisel3.domain
package chisel3.domains
package chisel3.experimental

Package for experimental features, which may have their API changed, be removed, etc.

Package for experimental features, which may have their API changed, be removed, etc.

Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.

Attributes

package chisel3.layers

This package contains common layer.Layers used by Chisel generators.

This package contains common layer.Layers used by Chisel generators.

Attributes

package chisel3.ltl
package chisel3.naming
package chisel3.probe
package chisel3.properties

The properties package includes functionality related to non-hardware data.

The properties package includes functionality related to non-hardware data.

This entire package is currently very experimental, so expect some rough edges and rapid API evolution.

Attributes

package chisel3.reflect
package chisel3.simulator
package chisel3.stage
package chisel3.test
package chisel3.testing
package chisel3.util

Type members

Classlikes

sealed abstract class ActualDirection(val value: Byte)

Resolved directions for both leaf and container nodes, only visible after a node is bound (since higher-level specifications like Input and Output can override directions).

Resolved directions for both leaf and container nodes, only visible after a node is bound (since higher-level specifications like Input and Output can override directions).

Attributes

Companion
object
Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Empty
object Input
object Output
object Unspecified
object ActualDirection

Attributes

Companion
class
Source
Data.scala
Supertypes
trait Sum
trait Mirror
class Object
trait Matchable
class Any
Self type
sealed trait Aggregate extends Data

An abstract class for data types that solely consist of (are an aggregate of) other Data objects.

An abstract class for data types that solely consist of (are an aggregate of) other Data objects.

Attributes

Source
Aggregate.scala
Supertypes
class Data
trait InstanceId
class Object
trait Matchable
class Any
Known subtypes
class Record
class DecodeBundle
class MixedVec[T]
class SparseVec[A]
class Bundle
class HWTuple10[A, B, C, D, E, F, G, H, I, J]
class HWTuple2[A, B]
class HWTuple3[A, B, C]
class HWTuple4[A, B, C, D]
class HWTuple5[A, B, C, D, E]
class HWTuple6[A, B, C, D, E, F]
class HWTuple7[A, B, C, D, E, F, G]
class HWTuple8[A, B, C, D, E, F, G, H]
class HWTuple9[A, B, C, D, E, F, G, H, I]
class PRNGIO
class ArbiterIO[T]
class PipeIO
class QueueIO[T]
class ReadyValidIO[T]
class DecoupledIO[T]
class IrrevocableIO[T]
class Valid[T]
class Vec[T]
Show all
class AliasedAggregateFieldException(message: String) extends ChiselException

Attributes

Source
Aggregate.scala
Supertypes
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
case class ArrayTestParam(value: Seq[TestParam]) extends TestParam

Attributes

Source
TestMarker.scala
Supertypes
trait Serializable
trait Product
trait Equals
class TestParam
class Object
trait Matchable
class Any
Show all
object AsyncReset

Attributes

Companion
class
Source
Bits.scala
Supertypes
class Object
trait Matchable
class Any
Self type
AsyncReset.type
sealed class AsyncReset(val width: Width = ...) extends Element, Reset

Data type representing asynchronous reset signals

Data type representing asynchronous reset signals

These signals are similar to Clocks in that they must be glitch-free for proper circuit operation. Regs defined with the implicit reset being an AsyncReset will be asychronously reset registers.

Attributes

Companion
object
Source
Bits.scala
Supertypes
trait Reset
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
class AutoClonetypeException(message: String) extends ChiselException

Attributes

Source
Aggregate.scala
Supertypes
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
case class BiConnectException(message: String) extends ChiselException

Attributes

Source
package.scala
Supertypes
trait Product
trait Equals
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
case class Binary(bits: Bits, width: FormatWidth = ...) extends FirrtlFormat

Format bits as Binary

Format bits as Binary

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class FirrtlFormat
class Printable
class Object
trait Matchable
class Any
Show all
class BindingException(message: String) extends ChiselException

Attributes

Source
package.scala
Supertypes
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
Known subtypes
sealed abstract class Bits(val width: Width)

Data type for binary bit vectors

Data type for binary bit vectors

The supertype for UInt and SInt. Note that the Bits factory method returns UInts.

Attributes

Companion
object
Source
Bits.scala
Supertypes
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class SInt
class UInt
class Bool
object Bits extends UIntFactory

Attributes

Companion
class
Source
Bits.scala
Supertypes
trait UIntFactory
class Object
trait Matchable
class Any
Self type
Bits.type
sealed class Bool() extends UInt, Reset

A data type for booleans, defined as a single bit indicating true or false.

A data type for booleans, defined as a single bit indicating true or false.

Attributes

Companion
object
Source
Bits.scala
Supertypes
trait Reset
class UInt
trait Num[UInt]
class Bits
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
object Bool extends BoolFactory

Attributes

Companion
class
Source
Bits.scala
Supertypes
trait BoolFactory
class Object
trait Matchable
class Any
Self type
Bool.type
trait BoolFactory

Attributes

Source
BoolFactory.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Bool
case object BuildInfo

Attributes

Source
BuildInfo.scala
Supertypes
trait Singleton
trait Product
trait Mirror
trait Serializable
trait Product
trait Equals
class Object
trait Matchable
class Any
Show all
Self type
BuildInfo.type
abstract class Bundle extends Record

Base class for data types defined as a bundle of other data types.

Base class for data types defined as a bundle of other data types.

Usage: extend this class (either as an anonymous or named class) and define members variables of Data subtypes to be elements in the Bundle.

Example of an anonymous IO bundle

 class MyModule extends Module {
   val io = IO(new Bundle {
     val in = Input(UInt(64.W))
     val out = Output(SInt(128.W))
   })
 }

Or as a named class

 class Packet extends Bundle {
   val header = UInt(16.W)
   val addr   = UInt(16.W)
   val data   = UInt(32.W)
 }
 class MyModule extends Module {
   val inPacket = IO(Input(new Packet))
   val outPacket = IO(Output(new Packet))
   val reg = Reg(new Packet)
   reg := inPacket
   outPacket := reg
 }

The fields of a Bundle are stored in an ordered Map called "elements" in reverse order of definition

 class MyBundle extends Bundle {
   val foo = UInt(8.W)
   val bar = UInt(8.W)
 }
 val wire = Wire(new MyBundle)
 wire.elements // VectorMap("bar" -> wire.bar, "foo" -> wire.foo)

Attributes

Source
Aggregate.scala
Supertypes
class Record
trait Selectable
trait Aggregate
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class HWTuple10[A, B, C, D, E, F, G, H, I, J]
class HWTuple2[A, B]
class HWTuple3[A, B, C]
class HWTuple4[A, B, C, D]
class HWTuple5[A, B, C, D, E]
class HWTuple6[A, B, C, D, E, F]
class HWTuple7[A, B, C, D, E, F, G]
class HWTuple8[A, B, C, D, E, F, G, H]
class HWTuple9[A, B, C, D, E, F, G, H, I]
class PRNGIO
class ArbiterIO[T]
class PipeIO
class QueueIO[T]
class ReadyValidIO[T]
class DecoupledIO[T]
class IrrevocableIO[T]
class Valid[T]
Show all
case class Character(bits: Bits) extends FirrtlFormat

Format bits as Character

Format bits as Character

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class FirrtlFormat
class Printable
class Object
trait Matchable
class Any
Show all
abstract class ChiselEnum

Attributes

Source
ChiselEnum.scala
Supertypes
class Object
trait Matchable
class Any
class ChiselException(message: String, cause: Throwable = ...) extends Exception

Attributes

Source
package.scala
Supertypes
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
Known subtypes
Show all
object Clock

Attributes

Companion
class
Source
Clock.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Clock.type
sealed class Clock extends Element

Attributes

Companion
object
Source
Clock.scala
Supertypes
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
object Const

Create a constant type in FIRRTL, which is guaranteed to take a single constant value.

Create a constant type in FIRRTL, which is guaranteed to take a single constant value.

Attributes

Source
Const.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Const.type
abstract class Data

This forms the root of the type system for wire data types. The data value must be representable as some number (need not be known at Chisel compile time) of bits, and must have methods to pack / unpack structured data to / from bits.

This forms the root of the type system for wire data types. The data value must be representable as some number (need not be known at Chisel compile time) of bits, and must have methods to pack / unpack structured data to / from bits.

Attributes

Companion
object
Source
Data.scala
Supertypes
trait InstanceId
class Object
trait Matchable
class Any
Known subtypes
trait OpaqueType
trait Aggregate
class Record
class DecodeBundle
class MixedVec[T]
class SparseVec[A]
class Bundle
class HWTuple10[A, B, C, D, E, F, G, H, I, J]
class HWTuple2[A, B]
class HWTuple3[A, B, C]
class HWTuple4[A, B, C, D]
class HWTuple5[A, B, C, D, E]
class HWTuple6[A, B, C, D, E, F]
class HWTuple7[A, B, C, D, E, F, G]
class HWTuple8[A, B, C, D, E, F, G, H]
class HWTuple9[A, B, C, D, E, F, G, H, I]
class PRNGIO
class ArbiterIO[T]
class PipeIO
class QueueIO[T]
class ReadyValidIO[T]
class DecoupledIO[T]
class IrrevocableIO[T]
class Valid[T]
class Vec[T]
class Element
class Type
class Analog
trait Property[T]
class AsyncReset
class Clock
object DontCare
class EnumType
class Type
trait Reset
class Bool
class ResetType
Show all
object Data

Attributes

Companion
class
Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Data.type
case class Decimal(bits: Bits, width: FormatWidth = ...) extends FirrtlFormat

Format bits as Decimal

Format bits as Decimal

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class FirrtlFormat
class Printable
class Object
trait Matchable
class Any
Show all
class Disable

API for handling disabling of simulation constructs

API for handling disabling of simulation constructs

Disables may be non-synthesizable so they can only be used for disabling simulation constructs

The default disable is the "hasBeenReset" of the currently in scope reset. It can be set by the user via the withDisable API

Users can access the current Disable with Module.disable

Attributes

Companion
object
Source
Disable.scala
Supertypes
class Object
trait Matchable
class Any
object Disable

Attributes

Companion
class
Source
Disable.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Disable.type
case object DontCare extends Element, ConnectableDocs

RHS (source) for Invalidate API. Causes connection logic to emit a DefInvalid when connected to an output port (or wire).

RHS (source) for Invalidate API. Causes connection logic to emit a DefInvalid when connected to an output port (or wire).

Attributes

Source
Data.scala
Supertypes
trait Singleton
trait Product
trait Mirror
trait Serializable
trait Product
trait Equals
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
Self type
DontCare.type
case class DoubleTestParam(value: Double) extends TestParam

Attributes

Source
TestMarker.scala
Supertypes
trait Serializable
trait Product
trait Equals
class TestParam
class Object
trait Matchable
class Any
Show all
sealed trait ElaboratedCircuit

The result of running Chisel elaboration

The result of running Chisel elaboration

Provides limited APIs for inspection of the resulting circuit.

Attributes

Companion
object
Source
ElaboratedCircuit.scala
Supertypes
class Object
trait Matchable
class Any
object ElaboratedCircuit

Attributes

Companion
trait
Source
ElaboratedCircuit.scala
Supertypes
class Object
trait Matchable
class Any
Self type
abstract class Element extends Data

Element is a leaf data type: it cannot contain other Data objects. Example uses are for representing primitive data types, like integers and bits.

Element is a leaf data type: it cannot contain other Data objects. Example uses are for representing primitive data types, like integers and bits.

Attributes

Source
Element.scala
Supertypes
class Data
trait InstanceId
class Object
trait Matchable
class Any
Known subtypes
class Type
class Analog
trait Property[T]
class AsyncReset
class Clock
object DontCare
class EnumType
class Type
trait Reset
class Bool
class ResetType
Show all
abstract class EnumType(val factory: ChiselEnum) extends Element

Attributes

Source
ChiselEnum.scala
Supertypes
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class Type
case class ExpectedAnnotatableException(message: String) extends BindingException

A function expected annotatable hardware

A function expected annotatable hardware

Attributes

Source
package.scala
Supertypes
trait Product
trait Equals
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
case class ExpectedChiselTypeException(message: String) extends BindingException

A function expected a Chisel type but got a hardware object

A function expected a Chisel type but got a hardware object

Attributes

Source
package.scala
Supertypes
trait Product
trait Equals
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
case class ExpectedHardwareException(message: String) extends BindingException

A function expected a hardware object but got a Chisel type

A function expected a hardware object but got a Chisel type

Attributes

Source
package.scala
Supertypes
trait Product
trait Equals
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
sealed abstract class FirrtlFormat(val specifier: Char) extends Printable

Superclass for Firrtl format specifiers for Bits

Superclass for Firrtl format specifiers for Bits

Attributes

Companion
object
Source
Printable.scala
Supertypes
class Printable
class Object
trait Matchable
class Any
Known subtypes
class Binary
class Character
class Decimal
class Hexadecimal
object FirrtlFormat

Attributes

Companion
class
Source
Printable.scala
Supertypes
trait Sum
trait Mirror
class Object
trait Matchable
class Any
Self type
sealed trait FixedIOBaseModule[A <: Data] extends BaseModule

A module or external module whose IO is generated from a specific generator. This module may have no additional IO created other than what is specified by its ioGenerator abstract member.

A module or external module whose IO is generated from a specific generator. This module may have no additional IO created other than what is specified by its ioGenerator abstract member.

Attributes

Source
FixedIOModule.scala
Supertypes
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class FixedIOExtModule[A]
class AutoBlackBox
class FixedIOModule[A]
class FixedIORawModule[A]
class CIRCTSRAM[T]
class TestHarness[M]
Show all
class FixedIOExtModule[A <: Data](val ioGenerator: A, params: Map[String, Param] = ...) extends ExtModule, FixedIOBaseModule[A]

A Chisel blackbox whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

A Chisel blackbox whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

Attributes

Source
FixedIOModule.scala
Supertypes
class ExtModule
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class AutoBlackBox
class FixedIOModule[A <: Data](val ioGenerator: A) extends Module, FixedIOBaseModule[A]

A Chisel module whose IO (in addition to clock and reset) is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

A Chisel module whose IO (in addition to clock and reset) is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

Attributes

Source
FixedIOModule.scala
Supertypes
class Module
class RawModule
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
class FixedIORawModule[A <: Data](val ioGenerator: A) extends RawModule, FixedIOBaseModule[A]

A Chisel module whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

A Chisel module whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

Attributes

Source
FixedIOModule.scala
Supertypes
class RawModule
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class CIRCTSRAM[T]
class TestHarness[M]
object FlatIO

The same as IO except there is no prefix when given a Record or Bundle. For Element (UInt, etc.) or Vec types, this is the same as IO. It is also the same as IO for chisel3.probe.Probe types.

The same as IO except there is no prefix when given a Record or Bundle. For Element (UInt, etc.) or Vec types, this is the same as IO. It is also the same as IO for chisel3.probe.Probe types.

Attributes

Example 
class MyBundle extends Bundle {
 val foo = Input(UInt(8.W))
 val bar = Output(UInt(8.W))
}
class MyModule extends Module {
 val io = FlatIO(new MyBundle)
 // input  [7:0] foo,
 // output [7:0] bar
}
Source
IO.scala
Supertypes
class Object
trait Matchable
class Any
Self type
FlatIO.type
object Flipped

Attributes

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Flipped.type
object FormalContract

Create a contract block.

Create a contract block.

Outside of verification uses, the arguments passed to the contract are simply returned as contract results. During formal verification, the contract may act as a cutpoint by returning symbolic values for its results and using the contract body as constraint.

Within the contract body, RequireProperty and EnsureProperty can be used to describe the pre and post-conditions of the contract. During formal verification, contracts can be used to divide large formal checks into smaller pieces by first asserting some local properties hold, and then assuming those properties hold in the context of the larger proof.

Attributes

Example

The following is a contract with no arguments.

FormalContract {
 RequireProperty(a >= 1)
 EnsureProperty(a + a >= 2)
}

The following is a contract with a single argument. It expresses the fact that the hardware implementation (a << 3) + a is equivalent to a * 9. During formal verification, this contract is interpreted as:

  • assert((a << 3) + a === a * 9) as a proof that the contract holds.
  • assume(b === a * 9) on a new symbolic value b as a simplification of other proofs.
val b = FormalContract((a << 3) + a) { b =>
 EnsureProperty(b === a * 9)
}

The following is a contract with multiple arguments. It expresses the fact that a carry-save adder with p, q, and r as inputs reduces the number of sum terms from p + q + r to c + s but doesn't change the sum of the terms. During formal verification, this contract is interpreted as:

  • assert(c + s === p + q + r) as a proof that the carry-save adder indeed compresses the three terms down to only two terms which have the same sum.
  • assume(u + v === p + q + r) on new symbolic values u and v as a simplification of other proofs.
val s = p ^ q ^ r
val c = (p & q | (p ^ q) & r) << 1
val (u, v) = FormalContract(c, s) { case (u, v) =>
 EnsureProperty(u + v === p + q + r)
}
Source
FormalContract.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object FormalTest

Attributes

Source
TestMarker.scala
Supertypes
class Object
trait Matchable
class Any
Self type
FormalTest.type
case class FullName(data: Data) extends Printable

Put full name within parent namespace (eg. bundleName.field)

Put full name within parent namespace (eg. bundleName.field)

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class Printable
class Object
trait Matchable
class Any
Show all
trait HasCustomConnectable

Trait to indicate that a subclass of Data has a custom Connectable.

Trait to indicate that a subclass of Data has a custom Connectable.

Users can implement the customConnectable method, which receives a default Connectable, and is expected to use the methods on Connectable to customize it. For example, a Bundle could define this by using connectable.Connectable.exclude to always exlude a specific member:

  class MyBundle extends Bundle with HasCustomConnectable {
    val foo = Bool()
    val bar = Bool()

    override def customConnectable[T <: Data](base: Connectable[T]): Connectable[T] = {
      base.exclude(_ => bar)
    }
  }

Attributes

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object HasTarget

Attributes

Companion
trait
Source
package.scala
Supertypes
trait Sum
trait Mirror
class Object
trait Matchable
class Any
Self type
HasTarget.type
sealed trait HasTarget

Exposes target information and suggestName functionality of a NamedComponent.

Exposes target information and suggestName functionality of a NamedComponent.

Attributes

Companion
object
Source
package.scala
Supertypes
class Object
trait Matchable
class Any
case class Hexadecimal(bits: Bits, width: FormatWidth = ...) extends FirrtlFormat

Format bits as Hexidecimal

Format bits as Hexidecimal

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class FirrtlFormat
class Printable
class Object
trait Matchable
class Any
Show all
case object HierarchicalModuleName extends Printable, SpecialFirrtlSubstitution

Represents the hierarchical name in the Verilog (%m)

Represents the hierarchical name in the Verilog (%m)

Attributes

Source
Printable.scala
Supertypes
trait Singleton
trait Product
trait Mirror
trait Serializable
trait Product
trait Equals
class Printable
class Object
trait Matchable
class Any
Show all
Self type
object IO

Attributes

Source
IO.scala
Supertypes
class Object
trait Matchable
class Any
Self type
IO.type
trait IgnoreSeqInBundle

Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.

Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.

Used to avoid raising an error/exception when a Seq is a public member of the bundle. This is useful if we those public Seq fields in the Bundle are unrelated to hardware construction.

Attributes

Source
Aggregate.scala
Supertypes
class Object
trait Matchable
class Any
Self type
trait ImplicitClock

Provides an implicit Clock for use within the RawModule

Provides an implicit Clock for use within the RawModule

Be careful to define the Clock value before trying to use it. Due to Scala initialization order, the actual val defining the Clock must occur before any uses of the implicit Clock.

Attributes

Example 
class MyModule extends RawModule with ImplicitClock {
 // Define a Clock value, it need not be called "implicitClock"
 val clk = IO(Input(Clock()))
 // Implement the virtual method to tell Chisel about this Clock value
 // Note that though this is a def, the actual Clock is assigned to a val (clk above)
 override protected def implicitClock = clk
 // Now we have a Clock to use in this RawModule
 val reg = Reg(UInt(8.W))
}
Source
Module.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class Module
class PRNG
class GaloisLFSR
trait LFSR
class Arbiter[T]
class LockingArbiter[T]
class LockingRRArbiter[T]
class RRArbiter[T]
class Pipe[T]
class Queue[T]
class FixedIOModule[A]
class TestHarness[M]
Show all
Self type
trait ImplicitReset

Provides an implicit Reset for use within the RawModule

Provides an implicit Reset for use within the RawModule

Be careful to define the Reset value before trying to use it. Due to Scala initialization order, the actual val defining the Reset object must occur before any uses of the implicit Reset.

Attributes

Example 
class MyModule extends RawModule with ImplicitReset {
 // Define a Reset value, it need not be called "implicitReset"
 val rst = IO(Input(AsyncReset()))
 // Implement the virtual method to tell Chisel about this Reset value
 // Note that though this is a def, the actual Reset is assigned to a val (rst above)
 override protected def implicitReset = clk
 // Now we have a Reset to use in this RawModule
 // Registers also require a clock
 val clock = IO(Input(Clock()))
 val reg = withClock(clock)(RegInit(0.U)) // Combine with ImplicitClock to get rid of this withClock
}
Source
Module.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class Module
class PRNG
class GaloisLFSR
trait LFSR
class Arbiter[T]
class LockingArbiter[T]
class LockingRRArbiter[T]
class RRArbiter[T]
class Pipe[T]
class Queue[T]
class FixedIOModule[A]
class TestHarness[M]
Show all
Self type
object Input

Input, Output, and Flipped are used to define the directions of Module IOs.

Input, Output, and Flipped are used to define the directions of Module IOs.

Note that they currently clone their source argument, including its bindings.

Thus, an error will be thrown if these are used on bound Data

Attributes

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Input.type
case class IntTestParam(value: BigInt) extends TestParam

Attributes

Source
TestMarker.scala
Supertypes
trait Serializable
trait Product
trait Equals
class TestParam
class Object
trait Matchable
class Any
Show all
class InternalErrorException(message: String, cause: Throwable = ...) extends ChiselException

Attributes

Source
package.scala
Supertypes
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
object Intrinsic

Attributes

Source
Intrinsic.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Intrinsic.type
object IntrinsicExpr

Attributes

Source
Intrinsic.scala
Supertypes
class Object
trait Matchable
class Any
Self type
sealed case class KnownWidth extends Width

Attributes

Companion
object
Source
Width.scala
Supertypes
trait Serializable
trait Product
trait Equals
class Width
class Object
trait Matchable
class Any
Show all
object KnownWidth

Attributes

Companion
class
Source
Width.scala
Supertypes
trait Product
trait Mirror
class Object
trait Matchable
class Any
Self type
KnownWidth.type
case class MapTestParam(value: Map[String, TestParam]) extends TestParam

Attributes

Source
TestMarker.scala
Supertypes
trait Serializable
trait Product
trait Equals
class TestParam
class Object
trait Matchable
class Any
Show all
object Mem

Attributes

Companion
class
Source
Mem.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Mem.type
sealed class Mem[T <: Data] extends MemBase[T]

A combinational/asynchronous-read, sequential/synchronous-write memory.

A combinational/asynchronous-read, sequential/synchronous-write memory.

Writes take effect on the rising clock edge after the request. Reads are combinational (requests will return data on the same cycle). Read-after-write hazards are not an issue.

Attributes

Note

when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)

Companion
object
Source
Mem.scala
Supertypes
class MemBase[T]
trait InstanceId
class Object
trait Matchable
class Any
Show all
sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt, val sourceInfo: SourceInfo)

Attributes

Source
Mem.scala
Supertypes
trait InstanceId
class Object
trait Matchable
class Any
Known subtypes
class Mem[T]
class SyncReadMem[T]
case class MixedDirectionAggregateException(message: String) extends BindingException

An aggregate had a mix of specified and unspecified directionality children

An aggregate had a mix of specified and unspecified directionality children

Attributes

Source
package.scala
Supertypes
trait Product
trait Equals
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
object Module

Attributes

Companion
class
Source
Module.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Module.type
abstract class Module extends RawModule, ImplicitClock, ImplicitReset

Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.

Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.

Attributes

Note

Module instantiations must be wrapped in a Module() call.

Companion
object
Source
Module.scala
Supertypes
class RawModule
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class PRNG
class GaloisLFSR
trait LFSR
class Arbiter[T]
class LockingArbiter[T]
class LockingRRArbiter[T]
class RRArbiter[T]
class Pipe[T]
class Queue[T]
class FixedIOModule[A]
Show all
case class MonoConnectException(message: String) extends ChiselException

Attributes

Source
package.scala
Supertypes
trait Product
trait Equals
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
object Mux

Attributes

Source
Mux.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Mux.type
case class Name(data: Data) extends Printable

Put innermost name (eg. field of bundle)

Put innermost name (eg. field of bundle)

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class Printable
class Object
trait Matchable
class Any
Show all
trait Num[T <: Data]

Abstract trait defining operations available on numeric-like hardware data types.

Abstract trait defining operations available on numeric-like hardware data types.

Type parameters

T

the underlying type of the number

Attributes

Companion
object
Source
Num.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class SInt
class UInt
class Bool
object Num extends NumObject

Convenience methods for converting between BigInts and Double and BigDecimal

Convenience methods for converting between BigInts and Double and BigDecimal

Attributes

Companion
trait
Source
Num.scala
Supertypes
trait NumObject
class Object
trait Matchable
class Any
Self type
Num.type
trait NumObject

NumObject has a lot of convenience methods for converting between BigInts and Double and BigDecimal

NumObject has a lot of convenience methods for converting between BigInts and Double and BigDecimal

Attributes

Source
Num.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Num
object Output

Attributes

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Output.type
case class PString(str: String) extends Printable

Wrapper for printing Scala Strings

Wrapper for printing Scala Strings

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class Printable
class Object
trait Matchable
class Any
Show all
case object Percent extends Printable

Represents escaped percents

Represents escaped percents

Attributes

Source
Printable.scala
Supertypes
trait Singleton
trait Product
trait Mirror
trait Serializable
trait Product
trait Equals
class Printable
class Object
trait Matchable
class Any
Show all
Self type
Percent.type
sealed abstract class Printable

Superclass of things that can be printed in the resulting circuit

Superclass of things that can be printed in the resulting circuit

Usually created using the custom string interpolator p"...". Printable string interpolation is similar to String interpolation in Scala For example:

 printf(p"The value of wire = $wire\n")

This is equivalent to writing:

 printf("The value of wire = %d\n", wire)

All Chisel data types have a method .toPrintable that gives a default pretty print that can be accessed via p"...". This works even for aggregate types, for example:

 val myVec = VecInit(5.U, 10.U, 13.U)
 printf(p"myVec = $myVec\n")
 // myVec = Vec(5, 10, 13)

 val myBundle = Wire(new Bundle {
   val foo = UInt()
   val bar = UInt()
 })
 myBundle.foo := 3.U
 myBundle.bar := 11.U
 printf(p"myBundle = $myBundle\n")
 // myBundle = Bundle(a -> 3, b -> 11)

Users can override the default behavior of .toPrintable in custom Bundle and Record types.

Attributes

Companion
object
Source
Printable.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class FirrtlFormat
class Binary
class Character
class Decimal
class Hexadecimal
class FullName
class Name
class PString
object Percent
class Printables
Show all
object Printable

Attributes

Companion
class
Source
Printable.scala
Supertypes
trait Sum
trait Mirror
class Object
trait Matchable
class Any
Self type
Printable.type
final implicit class PrintableHelper(val sc: StringContext) extends AnyVal

Implicit for custom Printable string interpolator

Implicit for custom Printable string interpolator

Attributes

Source
package.scala
Supertypes
class AnyVal
trait Matchable
class Any
case class Printables(pables: Iterable[Printable]) extends Printable

Attributes

Source
Printable.scala
Supertypes
trait Serializable
trait Product
trait Equals
class Printable
class Object
trait Matchable
class Any
Show all
trait Public

A trait that can be mixed into a Chisel module to indicate that a module has external users.

A trait that can be mixed into a Chisel module to indicate that a module has external users.

This will result in a public FIRRTL module being produced.

Attributes

Source
Public.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class TestHarness[M]
Self type
abstract class RawModule extends BaseModule

Abstract base class for Modules that contain Chisel RTL. This abstract base class is a user-defined module which does not include implicit clock and reset and supports multiple IO() declarations.

Abstract base class for Modules that contain Chisel RTL. This abstract base class is a user-defined module which does not include implicit clock and reset and supports multiple IO() declarations.

Attributes

Source
RawModule.scala
Supertypes
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class AllUnitTests
class FixedIORawModule[A]
class CIRCTSRAM[T]
class TestHarness[M]
class Module
class PRNG
class GaloisLFSR
trait LFSR
class Arbiter[T]
class LockingArbiter[T]
class LockingRRArbiter[T]
class RRArbiter[T]
class Pipe[T]
class Queue[T]
class FixedIOModule[A]
Show all
case class RebindingException(message: String) extends BindingException

Attempted to re-bind an already bound (directionality or hardware) object

Attempted to re-bind an already bound (directionality or hardware) object

Attributes

Source
package.scala
Supertypes
trait Product
trait Equals
class Exception
class Throwable
trait Serializable
class Object
trait Matchable
class Any
Show all
abstract class Record extends Aggregate, Selectable

Base class for Aggregates based on key values pairs of String and Data

Base class for Aggregates based on key values pairs of String and Data

Record should only be extended by libraries and fairly sophisticated generators. RTL writers should use Bundle. See Record#elements for an example.

Attributes

Source
Aggregate.scala
Supertypes
trait Selectable
trait Aggregate
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class DecodeBundle
class MixedVec[T]
class SparseVec[A]
class Bundle
class HWTuple10[A, B, C, D, E, F, G, H, I, J]
class HWTuple2[A, B]
class HWTuple3[A, B, C]
class HWTuple4[A, B, C, D]
class HWTuple5[A, B, C, D, E]
class HWTuple6[A, B, C, D, E, F]
class HWTuple7[A, B, C, D, E, F, G]
class HWTuple8[A, B, C, D, E, F, G, H]
class HWTuple9[A, B, C, D, E, F, G, H, I]
class PRNGIO
class ArbiterIO[T]
class PipeIO
class QueueIO[T]
class ReadyValidIO[T]
class DecoupledIO[T]
class IrrevocableIO[T]
class Valid[T]
Show all
object Reg

Utility for constructing hardware registers

Utility for constructing hardware registers

The width of a Reg (inferred or not) is copied from the type template

val r0 = Reg(UInt()) // width is inferred
val r1 = Reg(UInt(8.W)) // width is set to 8

val r2 = Reg(Vec(4, UInt())) // width is inferred
val r3 = Reg(Vec(4, UInt(8.W))) // width of each element is set to 8

class MyBundle {
 val unknown = UInt()
 val known   = UInt(8.W)
}
val r4 = Reg(new MyBundle)
// Width of r4.unknown is inferred
// Width of r4.known is set to 8

Attributes

Source
Reg.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Reg.type
object RegInit

Utility for constructing hardware registers with an initialization value.

Utility for constructing hardware registers with an initialization value.

The register is set to the initialization value when the current implicit reset is high

The two forms of RegInit differ in how the type and width of the resulting Reg are specified.

==Single Argument== The single argument form uses the argument to specify both the type and reset value. For non-literal Bits, the width of the Reg will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:

  1. Literal Bits initializer: width will be set to match
val r1 = RegInit(1.U) // width will be inferred to be 1
val r2 = RegInit(1.U(8.W)) // width is set to 8
  1. Non-Literal Element initializer - width will be inferred
val x = Wire(UInt())
val y = Wire(UInt(8.W))
val r1 = RegInit(x) // width will be inferred
val r2 = RegInit(y) // width will be inferred
  1. Aggregate initializer - width will be set to match the aggregate
class MyBundle extends Bundle {
 val unknown = UInt()
 val known   = UInt(8.W)
}
val w1 = Reg(new MyBundle)
val w2 = RegInit(w1)
// Width of w2.unknown is inferred
// Width of w2.known is set to 8

==Double Argument== The double argument form allows the type of the Reg and the default connection to be specified independently.

The width inference semantics for RegInit with two arguments match those of Reg. The first argument to RegInit is the type template which defines the width of the Reg in exactly the same way as the only argument to Wire.

More explicitly, you can reason about RegInit with multiple arguments as if it were defined as:

def RegInit[T <: Data](t: T, init: T): T = {
 val x = Reg(t)
 x := init
 x
}

Attributes

Source
Reg.scala
Supertypes
class Object
trait Matchable
class Any
Self type
RegInit.type
object RegNext

Utility for constructing one-cycle delayed versions of signals

Utility for constructing one-cycle delayed versions of signals

''The width of a RegNext is not set based on the next or init connections'' for Element types. In the following example, the width of bar will not be set and will be inferred by the FIRRTL compiler.

val foo = Reg(UInt(4.W))         // width is 4
val bar = RegNext(foo)           // width is unset

If you desire an explicit width, do not use RegNext and instead use a register with a specified width:

val foo = Reg(UInt(4.W))         // width is 4
val bar = Reg(chiselTypeOf(foo)) // width is 4
bar := foo

Also note that a RegNext of a Bundle ''will have it's width set'' for Aggregate types.

class MyBundle extends Bundle {
 val x = UInt(4.W)
}
val foo = Wire(new MyBundle)     // the width of foo.x is 4
val bar = RegNext(foo)           // the width of bar.x is 4

Attributes

Source
Reg.scala
Supertypes
class Object
trait Matchable
class Any
Self type
RegNext.type
trait RequireAsyncReset extends Module

Enforce that the Module.reset be Asynchronous (AsyncReset)

Enforce that the Module.reset be Asynchronous (AsyncReset)

Attributes

Source
RawModule.scala
Supertypes
class Module
class RawModule
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
trait RequireSyncReset extends Module

Enforce that the Module.reset be Synchronous (Bool)

Enforce that the Module.reset be Synchronous (Bool)

Attributes

Source
RawModule.scala
Supertypes
class Module
class RawModule
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
sealed trait Reset extends Element

Attributes

Companion
object
Source
Bits.scala
Supertypes
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class AsyncReset
class Bool
class ResetType
object Reset

Attributes

Companion
trait
Source
Bits.scala
Supertypes
class Object
trait Matchable
class Any
Self type
Reset.type
final class ResetType(val width: Width = ...) extends Reset

"Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool

"Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool

Attributes

Note

This shares a common interface with AsyncReset and Bool but is not their actual super type due to Bool inheriting from abstract class UInt

Source
Bits.scala
Supertypes
trait Reset
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
sealed class SInt extends Bits, Num[SInt]

A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.

A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.

Attributes

Companion
object
Source
Bits.scala
Supertypes
trait Num[SInt]
class Bits
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
object SInt extends SIntFactory

Attributes

Companion
class
Source
Bits.scala
Supertypes
trait SIntFactory
class Object
trait Matchable
class Any
Self type
SInt.type
trait SIntFactory

Attributes

Source
SIntFactory.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object SInt
sealed trait SimLog

A file or I/O device to print to in simulation

A file or I/O device to print to in simulation

val log = SimLog.file("logfile.log")
log.printf(cf"in = $in%0d\n")

val stderr = SimLog.StdErr
stderr.printf(cf"in = $in%0d\n")

// SimLog filenames themselves can be Printable.
// Be careful to avoid uninitialized registers.
val idx = Wire(UInt(8.W))
val log2 = SimLog.file(cf"logfile_$idx%0d.log")
log2.printf(cf"in = $in%0d\n")

Attributes

Companion
object
Source
SimLog.scala
Supertypes
class Object
trait Matchable
class Any
object SimLog

Attributes

Companion
trait
Source
SimLog.scala
Supertypes
trait Sum
trait Mirror
class Object
trait Matchable
class Any
Self type
SimLog.type
object SimulationTest

Attributes

Source
TestMarker.scala
Supertypes
class Object
trait Matchable
class Any
Self type
abstract class SimulationTestHarness extends FixedIORawModule[SimulationTestHarnessIO], SimulationTestHarnessInterface, ImplicitClock, ImplicitReset, Public

A fixed-IO module with the clock/init/done/success test interface that downstream test drivers such as ChiselSim and circt-test expect. Sets the implicit clock and reset.

A fixed-IO module with the clock/init/done/success test interface that downstream test drivers such as ChiselSim and circt-test expect. Sets the implicit clock and reset.

Attributes

Source
SimulationTestHarness.scala
Supertypes
trait Public
class FixedIORawModule[SimulationTestHarnessIO]
trait FixedIOBaseModule[SimulationTestHarnessIO]
class RawModule
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class TestHarness[M]
trait SimulationTestHarnessInterface

IO that reports the status of the test implemented by a testharness.

IO that reports the status of the test implemented by a testharness.

Attributes

Source
SimulationTestHarness.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class TestHarness[M]
case object SimulationTime extends Printable, SpecialFirrtlSubstitution

Represents the simulation time in the Verilog, similar to %t + $time

Represents the simulation time in the Verilog, similar to %t + $time

Attributes

Source
Printable.scala
Supertypes
trait Singleton
trait Product
trait Mirror
trait Serializable
trait Product
trait Equals
class Printable
class Object
trait Matchable
class Any
Show all
Self type
trait SourceInfoDoc

Does nothing

Does nothing

Attributes

Source
SourceInfoDoc.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Definition
object Instance
object ProbeValue
object RWProbe
object RWProbeValue
trait VecFactory
object Vec
Show all
sealed trait SpecialFirrtlSubstitution

Printable with special representation in FIRRTL

Printable with special representation in FIRRTL

Attributes

Note

The name of the singleton object exactly matches the FIRRTL value.

Source
Printable.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
Self type
Singleton & Printable
sealed abstract class SpecifiedDirection(val value: Byte)

User-specified directions.

User-specified directions.

Attributes

Companion
object
Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Flip
object Input
object Output
object Unspecified
object SpecifiedDirection

Attributes

Companion
class
Source
Data.scala
Supertypes
trait Sum
trait Mirror
class Object
trait Matchable
class Any
Self type
case class StringTestParam(value: String) extends TestParam

Attributes

Source
TestMarker.scala
Supertypes
trait Serializable
trait Product
trait Equals
class TestParam
class Object
trait Matchable
class Any
Show all
object SyncReadMem

Attributes

Companion
class
Source
Mem.scala
Supertypes
class Object
trait Matchable
class Any
Self type
sealed class SyncReadMem[T <: Data] extends MemBase[T]

A sequential/synchronous-read, sequential/synchronous-write memory.

A sequential/synchronous-read, sequential/synchronous-write memory.

Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.

Attributes

Note

when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)

Companion
object
Source
Mem.scala
Supertypes
class MemBase[T]
trait InstanceId
class Object
trait Matchable
class Any
Show all
sealed abstract class TestParam

Parameters for test declarations.

Parameters for test declarations.

Attributes

Source
TestMarker.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class IntTestParam
class MapTestParam
sealed class UInt extends Bits, Num[UInt]

A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.

A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.

Attributes

Companion
object
Source
Bits.scala
Supertypes
trait Num[UInt]
class Bits
class Element
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
class Bool
object UInt extends UIntFactory

Attributes

Companion
class
Source
Bits.scala
Supertypes
trait UIntFactory
class Object
trait Matchable
class Any
Self type
UInt.type
trait UIntFactory

Attributes

Source
UIntFactory.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Bits
object UInt
object UnitTests

Utility to discover and generate all unit tests in the classpath.

Utility to discover and generate all unit tests in the classpath.

Attributes

Source
UnitTestMain.scala
Supertypes
class Object
trait Matchable
class Any
Self type
UnitTests.type
case object UnknownWidth extends Width

Attributes

Source
Width.scala
Supertypes
trait Singleton
trait Product
trait Mirror
trait Serializable
trait Product
trait Equals
class Width
class Object
trait Matchable
class Any
Show all
Self type
sealed class Vec[T <: Data] extends Aggregate, VecLike[T]

A vector (array) of Data elements. Provides hardware versions of various collection transformation functions found in software array implementations.

A vector (array) of Data elements. Provides hardware versions of various collection transformation functions found in software array implementations.

Careful consideration should be given over the use of Vec vs Seq or some other Scala collection. In general Vec only needs to be used when there is a need to express the hardware collection in a Reg or IO Bundle or when access to elements of the array is indexed via a hardware signal.

Example of indexing into a Vec using a hardware address and where the Vec is defined in an IO Bundle

  val io = IO(new Bundle {
    val in = Input(Vec(20, UInt(16.W)))
    val addr = Input(UInt(5.W))
    val out = Output(UInt(16.W))
  })
  io.out := io.in(io.addr)

Type parameters

T

type of elements

Attributes

Note
  • when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
  • Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
Companion
object
Source
Aggregate.scala
Supertypes
trait VecLike[T]
trait IndexedSeq[T]
trait IndexedSeqOps[T, IndexedSeq, IndexedSeq[T]]
trait IndexedSeq[T]
trait IndexedSeqOps[T, IndexedSeq, IndexedSeq[T]]
trait Seq[T]
trait SeqOps[T, IndexedSeq, IndexedSeq[T]]
trait Seq[T]
trait Equals
trait SeqOps[T, IndexedSeq, IndexedSeq[T]]
trait PartialFunction[Int, T]
trait Int => T
trait Iterable[T]
trait Iterable[T]
trait IterableFactoryDefaults[T, IndexedSeq]
trait IterableOps[T, IndexedSeq, IndexedSeq[T]]
trait IterableOnceOps[T, IndexedSeq, IndexedSeq[T]]
trait IterableOnce[T]
trait Aggregate
class Data
trait InstanceId
class Object
trait Matchable
class Any
Show all
object Vec extends VecFactory

Attributes

Companion
class
Source
Aggregate.scala
Supertypes
trait VecFactory
class Object
trait Matchable
class Any
Self type
Vec.type
trait VecFactory extends SourceInfoDoc

Attributes

Source
Aggregate.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Vec
object VecInit

Attributes

Source
Aggregate.scala
Supertypes
class Object
trait Matchable
class Any
Self type
VecInit.type
trait VecLike[T <: Data] extends IndexedSeq[T]

A trait for Vecs containing common hardware generators for collection operations.

A trait for Vecs containing common hardware generators for collection operations.

Attributes

Source
Aggregate.scala
Supertypes
trait InstanceId
trait IndexedSeq[T]
trait IndexedSeqOps[T, IndexedSeq, IndexedSeq[T]]
trait IndexedSeq[T]
trait IndexedSeqOps[T, IndexedSeq, IndexedSeq[T]]
trait Seq[T]
trait SeqOps[T, IndexedSeq, IndexedSeq[T]]
trait Seq[T]
trait Equals
trait SeqOps[T, IndexedSeq, IndexedSeq[T]]
trait PartialFunction[Int, T]
trait Int => T
trait Iterable[T]
trait Iterable[T]
trait IterableFactoryDefaults[T, IndexedSeq]
trait IterableOps[T, IndexedSeq, IndexedSeq[T]]
trait IterableOnceOps[T, IndexedSeq, IndexedSeq[T]]
trait IterableOnce[T]
class Object
trait Matchable
class Any
Show all
Known subtypes
class Vec[T]
trait VerifPrintMacrosDoc

Attributes

Source
VerificationStatementIntf.scala
Supertypes
class Object
trait Matchable
class Any
object VerifStmtMacrosCompat

Attributes

Source
VerificationStatementMacros.scala
Supertypes
class Object
trait Matchable
class Any
Self type
abstract class VerificationStatement

Base class for all verification statements: Assert, Assume, Cover, Stop and Printf.

Base class for all verification statements: Assert, Assume, Cover, Stop and Printf.

Attributes

Source
VerificationStatement.scala
Supertypes
trait InstanceId
class Object
trait Matchable
class Any
Known subtypes
class Assert
class Assume
class Cover
class Printf
class Stop
final class WhenContext

A WhenContext may represent a when, and elsewhen, or an otherwise. Since FIRRTL does not have an "elsif" statement, alternatives must be mapped to nested if-else statements inside the alternatives of the preceeding condition. In order to emit proper FIRRTL, it is necessary to keep track of the depth of nesting of the FIRRTL whens. Due to the "thin frontend" nature of Chisel3, it is not possible to know if a when or elsewhen has a succeeding elsewhen or otherwise; therefore, this information is added by preprocessing the command queue.

A WhenContext may represent a when, and elsewhen, or an otherwise. Since FIRRTL does not have an "elsif" statement, alternatives must be mapped to nested if-else statements inside the alternatives of the preceeding condition. In order to emit proper FIRRTL, it is necessary to keep track of the depth of nesting of the FIRRTL whens. Due to the "thin frontend" nature of Chisel3, it is not possible to know if a when or elsewhen has a succeeding elsewhen or otherwise; therefore, this information is added by preprocessing the command queue.

Attributes

Source
When.scala
Supertypes
class Object
trait Matchable
class Any
object Width

Attributes

Companion
class
Source
Width.scala
Supertypes
trait Sum
trait Mirror
class Object
trait Matchable
class Any
Self type
Width.type
sealed abstract class Width

Attributes

Companion
object
Source
Width.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
class KnownWidth
object UnknownWidth
object Wire extends WireFactory

Utility for constructing hardware wires

Utility for constructing hardware wires

The width of a Wire (inferred or not) is copied from the type template

val w0 = Wire(UInt()) // width is inferred
val w1 = Wire(UInt(8.W)) // width is set to 8

val w2 = Wire(Vec(4, UInt())) // width is inferred
val w3 = Wire(Vec(4, UInt(8.W))) // width of each element is set to 8

class MyBundle {
 val unknown = UInt()
 val known   = UInt(8.W)
}
val w4 = Wire(new MyBundle)
// Width of w4.unknown is inferred
// Width of w4.known is set to 8

Attributes

Source
Data.scala
Supertypes
trait WireFactory
class Object
trait Matchable
class Any
Self type
Wire.type
object WireDefault

Utility for constructing hardware wires with a default connection

Utility for constructing hardware wires with a default connection

The two forms of WireDefault differ in how the type and width of the resulting Wire are specified.

==Single Argument== The single argument form uses the argument to specify both the type and default connection. For non-literal Bits, the width of the Wire will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:

  1. Literal Bits initializer: width will be set to match
val w1 = WireDefault(1.U) // width will be inferred to be 1
val w2 = WireDefault(1.U(8.W)) // width is set to 8
  1. Non-Literal Element initializer - width will be inferred
val x = Wire(UInt())
val y = Wire(UInt(8.W))
val w1 = WireDefault(x) // width will be inferred
val w2 = WireDefault(y) // width will be inferred
  1. Aggregate initializer - width will be set to match the aggregate
class MyBundle {
 val unknown = UInt()
 val known   = UInt(8.W)
}
val w1 = Wire(new MyBundle)
val w2 = WireDefault(w1)
// Width of w2.unknown is inferred
// Width of w2.known is set to 8

==Double Argument== The double argument form allows the type of the Wire and the default connection to be specified independently.

The width inference semantics for WireDefault with two arguments match those of Wire. The first argument to WireDefault is the type template which defines the width of the Wire in exactly the same way as the only argument to Wire.

More explicitly, you can reason about WireDefault with multiple arguments as if it were defined as:

def WireDefault[T <: Data](t: T, init: T): T = {
 val x = Wire(t)
 x := init
 x
}

Attributes

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
trait WireFactory

Attributes

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
object Wire
object WireInit

Utility for constructing hardware wires with a default connection

Utility for constructing hardware wires with a default connection

Alias for WireDefault.

Attributes

Note

The Init in WireInit refers to a "default" connection. This is in contrast to RegInit where the Init refers to a value on reset.

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
WireInit.type
object assert

Attributes

Source
VerificationStatement.scala
Supertypes
class Object
trait Matchable
class Any
Self type
assert.type
object assume

Attributes

Source
VerificationStatement.scala
Supertypes
class Object
trait Matchable
class Any
Self type
assume.type
object chiselTypeOf

Returns the chisel type of a hardware object, allowing other hardware to be constructed from it.

Returns the chisel type of a hardware object, allowing other hardware to be constructed from it.

Attributes

Source
Data.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object cover

Attributes

Source
VerificationStatement.scala
Supertypes
class Object
trait Matchable
class Any
Self type
cover.type
object dontTouch

Marks that a signal's leaves are an optimization barrier to Chisel and the FIRRTL compiler. This has the effect of guaranteeing that a signal will not be removed.

Marks that a signal's leaves are an optimization barrier to Chisel and the FIRRTL compiler. This has the effect of guaranteeing that a signal will not be removed.

Attributes

Note

Because this is an optimization barrier, constants will not be propagated through a signal's leaves marked as dontTouch.

Example 
class MyModule extends Module {
 val io = IO(new Bundle {
   val a = Input(UInt(32.W))
   val b = Output(UInt(32.W))
 })
 io.b := io.a
 val dead = io.a +% 1.U // normally dead would be pruned by DCE
 dontTouch(dead) // Marking it as such will preserve it
}
Source
dontTouch.scala
Supertypes
class Object
trait Matchable
class Any
Self type
dontTouch.type
object emitVerilog

Attributes

Source
verilog.scala
Supertypes
class Object
trait Matchable
class Any
Self type
implicit class fromBigIntToLiteral(bigint: BigInt)

These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.

These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.

Also provides .asBool to scala.Boolean and .asUInt to String

Note that, for stylistic reasons, one should avoid extracting immediately after this call using apply, ie. 0.asUInt(1)(0) due to potential for confusion (the 1 is a bit length and the 0 is a bit extraction position). Prefer storing the result and then extracting from it.

Attributes

Source
package.scala
Supertypes
class Object
trait Matchable
class Any
Known subtypes
implicit class fromBooleanToLiteral(boolean: Boolean)

Attributes

Source
package.scala
Supertypes
class Object
trait Matchable
class Any
implicit class fromIntToLiteral(int: Int) extends fromBigIntToLiteral

Attributes

Source
package.scala
Supertypes
class Object
trait Matchable
class Any
implicit class fromIntToWidth(int: Int)

Attributes

Source
package.scala
Supertypes
class Object
trait Matchable
class Any
implicit class fromLongToLiteral(long: Long) extends fromBigIntToLiteral

Attributes

Source
package.scala
Supertypes
class Object
trait Matchable
class Any
implicit class fromStringToLiteral(str: String)

Attributes

Source
package.scala
Supertypes
class Object
trait Matchable
class Any
object getVerilogString

Attributes

Source
verilog.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object layer

This object contains Chisel language features for creating layers. Layers are collections of hardware that are not always present in the circuit. Layers are intended to be used to hold verification or debug code.

This object contains Chisel language features for creating layers. Layers are collections of hardware that are not always present in the circuit. Layers are intended to be used to hold verification or debug code.

Attributes

Source
Layer.scala
Supertypes
class Object
trait Matchable
class Any
Self type
layer.type
object noModulePrefix

Creates a block under which any generator that gets run results in a module whose name does not have any module prefix applied.

Creates a block under which any generator that gets run results in a module whose name does not have any module prefix applied.

Attributes

Source
Module.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object printf

Prints a message in simulation

Prints a message in simulation

See apply methods for use

Attributes

Source
Printf.scala
Supertypes
class Object
trait Matchable
class Any
Self type
printf.type
object stop

Attributes

Source
VerificationStatement.scala
Supertypes
class Object
trait Matchable
class Any
Self type
stop.type
object suppressEnumCastWarning

Suppress enum cast warnings

Suppress enum cast warnings

Users should use &lt;EnumType&gt;.safe when possible.

This is primarily used for casting from UInt to a Bundle type that contains an Enum.

class MyBundle extends Bundle {
 val addr = UInt(8.W)
 val op = OpEnum()
}

// Since this is a cast to a Bundle, cannot use OpCode.safe
val bundle = suppressEnumCastWarning {
 someUInt.asTypeOf(new MyBundle)
}

Attributes

Source
ChiselEnum.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object when

Attributes

Source
When.scala
Supertypes
class Object
trait Matchable
class Any
Self type
when.type
object withClock

Attributes

Source
MultiClock.scala
Supertypes
class Object
trait Matchable
class Any
Self type
withClock.type
object withClockAndReset

Attributes

Source
MultiClock.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object withDisable

Creates a new Disable scope

Creates a new Disable scope

Attributes

Source
Disable.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object withModulePrefix

Creates a block under which any generator that gets run results in a module whose name is prepended with the given prefix.

Creates a block under which any generator that gets run results in a module whose name is prepended with the given prefix.

Attributes

Source
Module.scala
Supertypes
class Object
trait Matchable
class Any
Self type
object withReset

Attributes

Source
MultiClock.scala
Supertypes
class Object
trait Matchable
class Any
Self type
withReset.type
object withoutIO

Attributes

Source
MultiClock.scala
Supertypes
class Object
trait Matchable
class Any
Self type
withoutIO.type

Deprecated classlikes

abstract class BlackBox(val params: Map[String, Param] = ..., val knownLayers: Seq[Layer] = ...)

Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

Attributes

Note

The parameters API is experimental and may change

Example

Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

IBUFDS #(.DIFF_TERM("TRUE"),
         .IOSTANDARD("DEFAULT")) ibufds (
 .IB(ibufds_IB),
 .I(ibufds_I),
 .O(ibufds_O)
);

To instantiate it, a BlackBox can be used like following:

import chisel3._
import chisel3.experimental._
// Example with Xilinx differential buffer IBUFDS
class IBUFDS extends BlackBox(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                 "IOSTANDARD" -> "DEFAULT"
                    )) {
 val io = IO(new Bundle {
   val O = Output(Clock()) // IO names will be the same
   val I = Input(Clock())  // (without 'io_' in prefix)
   val IB = Input(Clock()) //
 })
}
Deprecated
[Since version 7.5.0] use `chisel3.ExtModule` instead. To migrate replace `val io = { ... }` with `val io = FlatIO { ... }`, `object io { ... }; locally { io }`, or manually flatten your IO as `ExtModule` allows calling `IO` more than once.
Source
BlackBox.scala
Supertypes
class BaseModule
trait Selectable
trait Selectable
trait InstanceId
class Object
trait Matchable
class Any
Show all
Known subtypes
trait InstanceId

Public API to access Node/Signal names. currently, the node's name, the full path name, and references to its parent Module and component. These are only valid once the design has been elaborated, and should not be used during its construction.

Public API to access Node/Signal names. currently, the node's name, the full path name, and references to its parent Module and component. These are only valid once the design has been elaborated, and should not be used during its construction.

Attributes

Deprecated
[Since version Chisel 6.7.0] User-defined annotations are not supported in CIRCT, use Targetable if you must.
Source
package.scala
Supertypes
class Object
trait Matchable
class Any

Types

type Connectable[T <: Data] = Connectable[T]

Attributes

Source
package.scala
type DoubleParam = DoubleParam

Attributes

Source
package.scala
type ExtModule = ExtModule

Attributes

Source
package.scala
type IntParam = IntParam

Attributes

Source
package.scala
type Param = Param

Attributes

Source
package.scala
type PrintableParam = PrintableParam

Attributes

Source
package.scala
type RawParam = RawParam

Attributes

Source
package.scala
type ReflectSelectable = Selectable

Attributes

Source
SelectableCompat.scala
type StringParam = StringParam

Attributes

Source
package.scala

Value members

Concrete methods

def getDataElements(a: Aggregate): Seq[Element]

Attributes

Source
package.scala
def withName[T](name: String)(nameMe: => T): T

Use Chisel's naming algorithm to name the returned value

Use Chisel's naming algorithm to name the returned value

This will name typical "nameable" things like Chisel Data, but only if the object is created in the thunk.

Type parameters

T

The type of the thing to be named

Value parameters

name

The name to use

nameMe

A thunk that returns the thing to be named

Attributes

Returns

The thing, possibly now named

Source
package.scala
def withNames[T <: Product](names: String*)(nameMe: => T): T

Use Chisel's naming algorithm to name values within the returned Product value

Use Chisel's naming algorithm to name values within the returned Product value

This will name typical "nameable" things like Chisel Data, but only for objects crated in the thunk.

Type parameters

T

The type of the thing to be named

Value parameters

nameMe

The scala.Product to be named

names

The names to use corresponding to interesting fields of the Product, empty Strings means no name

Attributes

Returns

The thing, with members possibly named

Source
package.scala

Concrete fields

val Connectable: Connectable.type

Attributes

Source
package.scala
val DoubleParam: DoubleParam.type

Attributes

Source
package.scala
val IntParam: IntParam.type

Attributes

Source
package.scala
val PrintableParam: PrintableParam.type

Attributes

Source
package.scala
val RawParam: RawParam.type

Attributes

Source
package.scala
val StringParam: StringParam.type

Attributes

Source
package.scala
final val deprecatedMFCMessage: "this feature will not be supported as part of the migration to the MLIR-based FIRRTL Compiler (MFC). For more information about this migration, please see the Chisel ROADMAP.md."

Attributes

Source
package.scala
final val deprecatedPublicAPIMsg: "APIs in chisel3.internal are not intended to be public"

Attributes

Source
package.scala

Extensions

Extensions

extension (b: Bundle)
def selectDynamic(field: String): Any

Unlike in Scala 2, in Scala 3 the compiler no longer infers the refined structural type for an anonymous subclass - it infers the unrefined type for anonymous Bundles, which will always be Bundle.

Unlike in Scala 2, in Scala 3 the compiler no longer infers the refined structural type for an anonymous subclass - it infers the unrefined type for anonymous Bundles, which will always be Bundle.

This extension method allows accessing elements of an anonymous Bundle even if its refined type is not inferred - without it the compiler will try to grab the element from class Bundle itself and will obviously error.

Attributes

Source
BundleSelect.scala

Implicits

Implicits

final implicit def PrintableHelper(sc: StringContext): PrintableHelper

Implicit for custom Printable string interpolator

Implicit for custom Printable string interpolator

Attributes

Source
package.scala
final implicit def fromBigIntToLiteral(bigint: BigInt): fromBigIntToLiteral

These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.

These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.

Also provides .asBool to scala.Boolean and .asUInt to String

Note that, for stylistic reasons, one should avoid extracting immediately after this call using apply, ie. 0.asUInt(1)(0) due to potential for confusion (the 1 is a bit length and the 0 is a bit extraction position). Prefer storing the result and then extracting from it.

Attributes

Source
package.scala
final implicit def fromBooleanToLiteral(boolean: Boolean): fromBooleanToLiteral

Attributes

Source
package.scala
final implicit def fromIntToLiteral(int: Int): fromIntToLiteral

Attributes

Source
package.scala
final implicit def fromIntToWidth(int: Int): fromIntToWidth

Attributes

Source
package.scala
final implicit def fromLongToLiteral(long: Long): fromLongToLiteral

Attributes

Source
package.scala
final implicit def fromStringToLiteral(str: String): fromStringToLiteral

Attributes

Source
package.scala
implicit def string2Printable(str: String): Printable

Attributes

Source
package.scala
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