doNotDedup

chisel3.experimental.doNotDedup
object doNotDedup

Marks that a module to be ignored in Dedup Transform in Firrtl pass

Attributes

Example
def fullAdder(a: UInt, b: UInt, myName: String): UInt = {
  val m = Module(new Module {
    val io = IO(new Bundle {
      val a = Input(UInt(32.W))
      val b = Input(UInt(32.W))
      val out = Output(UInt(32.W))
    })
    override def desiredName = "adder_" + myNname
    io.out := io.a + io.b
  })
  doNotDedup(m)
  m.io.a := a
  m.io.b := b
  m.io.out
}
class AdderTester extends Module
with ConstantPropagationTest {
val io = IO(new Bundle {
  val a = Input(UInt(32.W))
  val b = Input(UInt(32.W))
  val out = Output(Vec(2, UInt(32.W)))
})
io.out(0) := fullAdder(io.a, io.b, "mod1")
io.out(1) := fullAdder(io.a, io.b, "mod2")
}
Source
Annotation.scala
Graph
Supertypes
class Object
trait Matchable
class Any
Self type
doNotDedup.type

Members list

Value members

Concrete methods

def apply[T <: RawModule](module: T): Unit

Marks a module to be ignored in Dedup Transform in Firrtl

Marks a module to be ignored in Dedup Transform in Firrtl

Value parameters

module

The module to be marked

Attributes

Returns

Unmodified signal module

Source
Annotation.scala