chisel
7.9.0+2-5294dafe-SNAPSHOT
API
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chisel/chisel3/chisel3.stage/chisel3.stage.phases

chisel3.stage.phases

package chisel3.stage.phases

Members list

Type members

Classlikes

class AddDedupGroupAnnotations extends Phase

Attributes

Source
AddDedupGroupAnnotations.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
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class AddImplicitOutputAnnotationFile extends Phase

Adds an firrtl.options.OutputAnnotationFileAnnotation if one does not exist. This replicates old behavior where an output annotation file was always written.

Adds an firrtl.options.OutputAnnotationFileAnnotation if one does not exist. This replicates old behavior where an output annotation file was always written.

Attributes

Source
AddImplicitOutputAnnotationFile.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
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class AddImplicitOutputFile extends Phase

Add a output file for a Chisel circuit, derived from the top module in the circuit, if no ChiselOutputFileAnnotation already exists.

Add a output file for a Chisel circuit, derived from the top module in the circuit, if no ChiselOutputFileAnnotation already exists.

Attributes

Source
AddImplicitOutputFile.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
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class AddSerializationAnnotations extends Phase

Adds stage.CircuitSerializationAnnotations based on ChiselOutputFileAnnotation

Adds stage.CircuitSerializationAnnotations based on ChiselOutputFileAnnotation

Attributes

Source
AddSerializationAnnotations.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
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class Checks extends Phase

Sanity checks an firrtl.AnnotationSeq before running the main firrtl.options.Phases of chisel3.stage.ChiselStage.

Sanity checks an firrtl.AnnotationSeq before running the main firrtl.options.Phases of chisel3.stage.ChiselStage.

Attributes

Source
Checks.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
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class Convert extends Phase

This prepares a `ChiselCircuitAnnotation for compilation with FIRRTL. This does three things:

This prepares a `ChiselCircuitAnnotation for compilation with FIRRTL. This does three things:

  • Uses chisel3.internal.firrtl.Converter to generate a FirrtlCircuitAnnotation`
  • Extracts all firrtl.annotations.Annotations from the chisel3.internal.firrtl.Circuit
  • Generates any needed RunFirrtlTransformAnnotations from extracted firrtl.annotations.Annotations

Attributes

Source
Convert.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
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class Elaborate extends Phase

Elaborate all chisel3.stage.ChiselGeneratorAnnotations into chisel3.stage.ChiselCircuitAnnotations.

Elaborate all chisel3.stage.ChiselGeneratorAnnotations into chisel3.stage.ChiselCircuitAnnotations.

Attributes

Source
Elaborate.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
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class Emitter extends Phase

Emit a chisel3.stage.ChiselCircuitAnnotation to a file if a chisel3.stage.ChiselOutputFileAnnotation is present.

Emit a chisel3.stage.ChiselCircuitAnnotation to a file if a chisel3.stage.ChiselOutputFileAnnotation is present.

Attributes

Todo

This should be switched to support correct emission of multiple circuits to multiple files.

Source
Emitter.scala
Supertypes
trait Phase
trait LazyLogging
class Object
trait Matchable
class Any
Show all
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