RegInit

Utility for constructing hardware registers with an initialization value.

The register is set to the initialization value when the current implicit reset is high

The two forms of RegInit differ in how the type and width of the resulting Reg are specified.

==Single Argument== The single argument form uses the argument to specify both the type and reset value. For non-literal Bits, the width of the Reg will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:

1. Literal Bits initializer: width will be set to match

val r1 = RegInit(1.U) // width will be inferred to be 1
val r2 = RegInit(1.U(8.W)) // width is set to 8

2. Non-Literal Element initializer - width will be inferred

val x = Wire(UInt())
val y = Wire(UInt(8.W))
val r1 = RegInit(x) // width will be inferred
val r2 = RegInit(y) // width will be inferred

3. Aggregate initializer - width will be set to match the aggregate

class MyBundle extends Bundle {
 val unknown = UInt()
 val known   = UInt(8.W)
}
val w1 = Reg(new MyBundle)
val w2 = RegInit(w1)
// Width of w2.unknown is inferred
// Width of w2.known is set to 8

==Double Argument== The double argument form allows the type of the Reg and the default connection to be specified independently.

The width inference semantics for RegInit with two arguments match those of Reg. The first argument to RegInit is the type template which defines the width of the Reg in exactly the same way as the only argument to Wire.

More explicitly, you can reason about RegInit with multiple arguments as if it were defined as:

def RegInit[T <: Data](t: T, init: T): T = {
 val x = Reg(t)
 x := init
 x
}