Randomization

Randomize everything

This will randomize everything that the FIRRTL/Verilog ABI allows. All Verilog that Chisel produces will have a random two-state value. Verilog that Chisel does not have control of (e.g., blackboxes) will be brought up in a different state unless they opt-in to the FIRRTL/Verilog ABI.

Non-two-state values (i.e., x)

Randomize nothing

This will cause the simulation to be brought up in whatever state the simulator brings up a simulation in. If the simulator supports x, then uninitialized hardware will be brought up in x. However, if the simulator is two-state (e.g., Verilator), then it will be brought up in a simulator-dependent state.