chisel/chisel3/chisel3.simulator/Settings

Settings

chisel3.simulator.Settings

See theSettings companion object

Settings for controlling ChiselSim simulations

These setings are only intended to be associated with Chisel, FIRRTL, and FIRRTL's Verilog ABI and not to do with lower-level control of the FIRRTL compilation itself or the Verilog compilation and simulation.

Value parameters

assertVerboseCond: a condition that guards the printing of assert messages created from circt_chisel_ifelsefatal intrinsics
enableWavesAtTimeZero: enable waveform dumping at time zero. This requires a simulator capable of dumping waves.
instanceChoices: Instance choice selections as (specializationTime, option, case) tuples. Use SpecializationTime.FirtoolCompilationTime to specialize during FIRRTL compilation, or SpecializationTime.VerilogElaborationTime to defer to Verilog elaboration time. Use this to select specific implementations for instance_choice operations.
layerControl: determines which chisel3.layer.Layers should be
libraries: Names of libraries to include in simulation. Use this to provide implementations for DPI functions, for example. The simulator will resolve these libraries to concrete files using the CHISELSIM_LIBS environment variable and chiselsim.libraries Java property.
libraryPaths: Paths to libraries to include in simulation. Use this to provide implementations for DPI functions, for example.
plusArgs: Verilog $value$plusargs or $test$plusargs to set at simulation runtime.
printfCond: a condition that guards printing of chisel3.printfs
randomization: random initialization settings to use
stopCond: a condition that guards terminating the simulation (via $fatal) for asserts created from circt_chisel_ifelsefatal intrinsics enabled during Verilog elaboration.