ClockDomain

A sequence of name--type pairs that define the schema for this domain.

The fields comprise the information that a user, after Verilog generation, should set in order to interact with, generate collateral files related to, or check the correctness of their choices for a domain.

Alternatively, the fields are the "parameters" for the domain. E.g., a clock domain could be parameterzied by an integer frequency. Chisel itself has no knowledge of this frequency, nor does it need a frequency to generate Verilog. However, in order to generate an implementation constraints file, the user must provide a frequency.

To change the fields from the default, override this method in your domain.

override def fields: Seq[(String, Field.Type)] = Seq(
 "foo" -> Field.Boolean
)

Construct a type of this domain kind.

For a given domain, this is used to create a Chisel type which can be used in a port. This is typically used to create domain type ports.

E.g., to create a chisel3.domains.ClockDomain port, use:

import chisel3.domains.ClockDomain

val A = IO(Input(ClockDomain.Type()))