Reg
chisel3.Reg
object Reg
Utility for constructing hardware registers
The width of a Reg (inferred or not) is copied from the type template
val r0 = Reg(UInt()) // width is inferred
val r1 = Reg(UInt(8.W)) // width is set to 8
val r2 = Reg(Vec(4, UInt())) // width is inferred
val r3 = Reg(Vec(4, UInt(8.W))) // width of each element is set to 8
class MyBundle {
val unknown = UInt()
val known = UInt(8.W)
}
val r4 = Reg(new MyBundle)
// Width of r4.unknown is inferred
// Width of r4.known is set to 8
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