ImplicitReset

Attributes

Example

class MyModule extends RawModule with ImplicitReset {
 // Define a Reset value, it need not be called "implicitReset"
 val rst = IO(Input(AsyncReset()))
 // Implement the virtual method to tell Chisel about this Reset value
 // Note that though this is a def, the actual Reset is assigned to a val (rst above)
 override protected def implicitReset = clk
 // Now we have a Reset to use in this RawModule
 // Registers also require a clock
 val clock = IO(Input(Clock()))
 val reg = withClock(clock)(RegInit(0.U)) // Combine with ImplicitClock to get rid of this withClock
}

Source

Module.scala

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Supertypes

class Object

trait Matchable

class Any

Known subtypes

class Module

class PRNG

class FibonacciLFSR

class MaxPeriodFibonacciLFSR

class GaloisLFSR

class MaxPeriodGaloisLFSR

trait LFSR

class Arbiter[T]

class LockingArbiterLike[T]

class LockingArbiter[T]

class LockingRRArbiter[T]

class RRArbiter[T]

class Pipe[T]

class Queue[T]

class FixedIOModule[A]

trait RequireAsyncReset

trait RequireSyncReset

class SimulationTestHarness

class TestHarness[M]

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Self type

RawModule