ShiftRegisters

chisel3.util.ShiftRegisters

Attributes

Source
Reg.scala
Graph
Supertypes
class Object
trait Matchable
class Any
Self type

Members list

Value members

Inherited methods

def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool)(using SourceInfo): Seq[T]

Returns delayed input signal registers with reset initialization from 1 to n.

Returns delayed input signal registers with reset initialization from 1 to n.

Value parameters

en

enable the shift

in

input to delay

n

number of cycles to delay

resetData

reset value for each register in the shift

Attributes

Inherited from:
ShiftRegistersIntf (hidden)
Source
RegIntf.scala
def apply[T <: Data](in: T, n: Int)(using SourceInfo): Seq[T]

Returns a sequence of delayed input signal registers from 1 to n.

Returns a sequence of delayed input signal registers from 1 to n.

Enable is assumed to be true.

Value parameters

in

input to delay

n

number of cycles to delay

Attributes

Inherited from:
ShiftRegistersIntf (hidden)
Source
RegIntf.scala
def apply[T <: Data](in: T, n: Int, en: Bool)(using SourceInfo): Seq[T]

Returns a sequence of delayed input signal registers from 1 to n.

Returns a sequence of delayed input signal registers from 1 to n.

Value parameters

en

enable the shift

in

input to delay

n

number of cycles to delay

Attributes

Inherited from:
ShiftRegistersIntf (hidden)
Source
RegIntf.scala