A sequential/synchronous-read, sequential/synchronous-write memory.
Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.
Attributes
- Note
-
when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)
- Companion
- object
- Source
- Mem.scala
- Graph
-
- Supertypes
-
class MemBase[T]trait InstanceIdtrait SourceInfoDocclass Objecttrait Matchableclass AnyShow all
Members list
Value members
Inherited methods
Attributes
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Creates a read/write accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.
Creates a read/write accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.
Attributes
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.
Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.
Attributes
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.
Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.
Attributes
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Compares the receiver object (this) with the argument object (that) for equivalence.
Compares the receiver object (this) with the argument object (that) for equivalence.
Any implementation of this method should be an equivalence relation:
- It is reflexive: for any instance
xof typeAny,x.equals(x)should returntrue. - It is symmetric: for any instances
xandyof typeAny,x.equals(y)should returntrueif and only ify.equals(x)returnstrue. - It is transitive: for any instances
x,y, andzof typeAnyifx.equals(y)returnstrueandy.equals(z)returnstrue, thenx.equals(z)should returntrue.
If you override this method, you should verify that your implementation remains an equivalence relation. Additionally, when overriding this method it is usually necessary to override hashCode to ensure that objects which are "equal" (o1.equals(o2) returns true) hash to the same scala.Int. (o1.hashCode.equals(o2.hashCode)).
Value parameters
- that
-
the object to compare against this object for equality.
Attributes
- Returns
-
trueif the receiver object is equivalent to the argument;falseotherwise. - Definition Classes
-
HasId -> Any
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Attributes
- Returns
-
Whether either autoName or suggestName has been called
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Calculates a hash code value for the object.
Calculates a hash code value for the object.
The default hashing algorithm is platform dependent.
Note that it is allowed for two objects to have identical hash codes (o1.hashCode.equals(o2.hashCode)) yet not be equal (o1.equals(o2) returns false). A degenerate implementation could always return 0. However, it is required that if two objects are equal (o1.equals(o2) returns true) that they have identical hash codes (o1.hashCode.equals(o2.hashCode)). Therefore, when overriding this method, be sure to verify that the behavior is consistent with the equals method.
Attributes
- Returns
-
the hash code value for this object.
- Definition Classes
-
HasId -> Any
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Attributes
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Attributes
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Attributes
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Attributes
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Attributes
- Inherited from:
- SyncReadMemIntf (hidden)
- Source
- MemIntf.scala
Attributes
- Inherited from:
- SyncReadMemIntf (hidden)
- Source
- MemIntf.scala
Attributes
- Definition Classes
-
SyncReadMemIntf
- Inherited from:
- SyncReadMemIntf (hidden)
- Source
- MemIntf.scala
Creates a read accessor into the memory with dynamic addressing. Takes a clock parameter to bind a clock that may be different from the implicit clock. See the class documentation of the memory for more detailed information.
Creates a read accessor into the memory with dynamic addressing. Takes a clock parameter to bind a clock that may be different from the implicit clock. See the class documentation of the memory for more detailed information.
Attributes
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element and a clock that may be different from the implicit clock.
Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element and a clock that may be different from the implicit clock.
Value parameters
- clock
-
clock to bind to this read-write port
- enable
-
enables access to the memory
- idx
-
memory element index to write into
- isWrite
-
performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true
- mask
-
the write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.
- writeData
-
new data to write
Attributes
- Returns
-
The read data Vec of the memory at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle
- Note
-
this is only allowed if the memory's element data type is a Vec
- Inherited from:
- SyncReadMemIntf (hidden)
- Source
- MemIntf.scala
Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element.
Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element.
Value parameters
- enable
-
enables access to the memory
- idx
-
memory element index to write into
- isWrite
-
performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true
- mask
-
the write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.
- writeData
-
new data to write
Attributes
- Returns
-
The read data Vec of the memory at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle
- Note
-
this is only allowed if the memory's element data type is a Vec
- Example
-
Controlling a read/masked write port with IO signals
class MyMaskedMemWrapper extends Module { val width = 2 val io = IO(new Bundle { val address = Input(UInt()) val wdata = Input(Vec(2, UInt(width.W))) val mask = Input(Vec(2, Bool())) val enable = Input(Bool()) val isWrite = Input(Bool()) val rdata = Output(Vec(2, UInt(width.W))) }) val mem = SyncReadMem(2, Vec(2, UInt(width.W))) io.rdata := mem.readWrite(io.address, io.wdata, io.mask, io.enable, io.isWrite) } - Inherited from:
- SyncReadMemIntf (hidden)
- Source
- MemIntf.scala
Generates an explicit read-write port for this SyncReadMem, using a clock that may be different from the implicit clock.
Generates an explicit read-write port for this SyncReadMem, using a clock that may be different from the implicit clock.
Value parameters
- clock
-
clock to bind to this read-write port
- enable
-
enables access to the memory
- idx
-
memory element index to write into
- isWrite
-
performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true
- writeData
-
new data to write
Attributes
- Returns
-
The read data of the memory, which gives the value at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle.
- Inherited from:
- SyncReadMemIntf (hidden)
- Source
- MemIntf.scala
Generates an explicit read-write port for this SyncReadMem. Note that this does not infer port directionality based on connection semantics and the when context unlike SyncReadMem.apply(), so the behavior of the port must be controlled by changing the values of the input parameters.
Generates an explicit read-write port for this SyncReadMem. Note that this does not infer port directionality based on connection semantics and the when context unlike SyncReadMem.apply(), so the behavior of the port must be controlled by changing the values of the input parameters.
Value parameters
- enable
-
enables access to the memory
- idx
-
memory element index to write into
- isWrite
-
performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true
- writeData
-
new data to write
Attributes
- Returns
-
The read data of the memory, which gives the value at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle.
- Example
-
Controlling a read/write port with IO signals
class MyMemWrapper extends Module { val width = 2 val io = IO(new Bundle { val address = Input(UInt()) val wdata = Input(UInt(width.W)) val enable = Input(Bool()) val isWrite = Input(Bool()) val rdata = Output(UInt(width.W)) }) val mem = SyncReadMem(2, UInt(width.W)) io.rdata := mem.readWrite(io.address, io.wdata, io.enable, io.isWrite) } - Inherited from:
- SyncReadMemIntf (hidden)
- Source
- MemIntf.scala
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
Value parameters
- seed
-
The seed for the name of this component
Attributes
- Returns
-
this object
- Inherited from:
- HasId (hidden)
- Source
- Builder.scala
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Attributes
- Inherited from:
- NamedComponent (hidden)
- Source
- Builder.scala
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
Attributes
- Note
-
Should not be called until circuit elaboration is complete
- Inherited from:
- NamedComponent (hidden)
- Source
- Builder.scala
Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.
Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.
If root is defined, the target is a hierarchical path starting from root.
If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.
Attributes
- Note
-
If
rootis defined, and has not finished elaboration, this must be called withinatModuleBodyEnd.The NamedComponent must be a descendant of
root, if it is defined.This doesn't have special handling for Views.
- Inherited from:
- NamedComponent (hidden)
- Source
- Builder.scala
Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.
Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.
If root is defined, the target is a hierarchical path starting from root.
If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.
Attributes
- Note
-
If
rootis defined, and has not finished elaboration, this must be called withinatModuleBodyEnd.The NamedComponent must be a descendant of
root, if it is defined.This doesn't have special handling for Views.
- Inherited from:
- NamedComponent (hidden)
- Source
- Builder.scala
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
Attributes
- Note
-
Should not be called until circuit elaboration is complete
- Inherited from:
- NamedComponent (hidden)
- Source
- Builder.scala
Creates a masked write accessor into the memory with a clock that may be different from the implicit clock.
Creates a masked write accessor into the memory with a clock that may be different from the implicit clock.
Value parameters
- clock
-
clock to bind to this accessor
- data
-
new data to write
- idx
-
memory element index to write into
- mask
-
write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.
Attributes
- Note
-
this is only allowed if the memory's element data type is a Vec
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Creates a masked write accessor into the memory.
Creates a masked write accessor into the memory.
Value parameters
- data
-
new data to write
- idx
-
memory element index to write into
- mask
-
write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.
Attributes
- Note
-
this is only allowed if the memory's element data type is a Vec
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Creates a write accessor into the memory with a clock that may be different from the implicit clock.
Creates a write accessor into the memory with a clock that may be different from the implicit clock.
Value parameters
- clock
-
clock to bind to this accessor
- data
-
new data to write
- idx
-
memory element index to write into
Attributes
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Creates a write accessor into the memory.
Creates a write accessor into the memory.
Value parameters
- data
-
new data to write
- idx
-
memory element index to write into
Attributes
- Inherited from:
- MemBaseIntf (hidden)
- Source
- MemIntf.scala
Concrete fields
Attributes
- Source
- Mem.scala