ChiselStage

circt.stage.ChiselStage
See theChiselStage companion class
object ChiselStage

Utilities for compiling Chisel

Attributes

Companion
class
Source
ChiselStage.scala
Graph
Supertypes
class Object
trait Matchable
class Any
Self type

Members list

Value members

Concrete methods

def elaborate(gen: => RawModule, args: Array[String] = ...): ElaboratedCircuit

Run elaboration and return the ElaboratedCircuit

Run elaboration and return the ElaboratedCircuit

Value parameters

args

additional command line arguments to pass to Chisel

gen

a call-by-name Chisel module

Attributes

Returns

the ElaboratedCircuit

Source
ChiselStage.scala
def emitBtor2(gen: => RawModule, args: Array[String] = ..., firtoolOpts: Array[String] = ...): String

Compile a Chisel circuit to btor2

Compile a Chisel circuit to btor2

Value parameters

args

additional command line arguments to pass to Chisel

firtoolOpts

additional command line options to pass to firtool

gen

a call-by-name Chisel module

Attributes

Returns

a string containing the btor2 output

Source
ChiselStage.scala
def emitCHIRRTL(gen: => RawModule, args: Array[String] = ...): String

Elaborate a Chisel circuit into a CHIRRTL string

Elaborate a Chisel circuit into a CHIRRTL string

Attributes

Source
ChiselStage.scala
def emitCHIRRTLFile(gen: => RawModule, args: Array[String] = ...): AnnotationSeq

Elaborates a Chisel circuit and emits it to a file

Elaborates a Chisel circuit and emits it to a file

Value parameters

args

additional command line arguments to pass to Chisel

gen

a call-by-name Chisel module

Attributes

Source
ChiselStage.scala
def emitFIRRTLDialect(gen: => RawModule, args: Array[String] = ..., firtoolOpts: Array[String] = ...): String

Compile a Chisel circuit to FIRRTL dialect

Compile a Chisel circuit to FIRRTL dialect

Attributes

Source
ChiselStage.scala
def emitHWDialect(gen: => RawModule, args: Array[String] = ..., firtoolOpts: Array[String] = ...): String

Compile a Chisel circuit to HWS dialect

Compile a Chisel circuit to HWS dialect

Attributes

Source
ChiselStage.scala
def emitSystemVerilog(gen: => RawModule, args: Array[String] = ..., firtoolOpts: Array[String] = ...): String

Compile a Chisel circuit to SystemVerilog

Compile a Chisel circuit to SystemVerilog

Value parameters

args

additional command line arguments to pass to Chisel

firtoolOpts

additional circt.stage.FirtoolOption to pass to firtool

gen

a call-by-name Chisel module

Attributes

Returns

a string containing the Verilog output

Source
ChiselStage.scala
def emitSystemVerilogFile(gen: => RawModule, args: Array[String] = ..., firtoolOpts: Array[String] = ...): AnnotationSeq

Compile a Chisel circuit to multiple SystemVerilog files.

Compile a Chisel circuit to multiple SystemVerilog files.

Value parameters

args

additional command line arguments to pass to Chisel

firtoolOpts

additional command line options to pass to firtool

gen

a call-by-name Chisel module

Attributes

Returns

the annotations that exist after compilation

Source
ChiselStage.scala

Deprecated methods

def convert(gen: => RawModule, args: Array[String] = ...): Circuit

Return a CHIRRTL circuit for a Chisel module

Return a CHIRRTL circuit for a Chisel module

Value parameters

gen

a call-by-name Chisel module

Attributes

Deprecated
[Since version Chisel 6.8.0] Use elaborate or one of the emit* methods instead
Source
ChiselStage.scala