chisel
7.9.0+2-5294dafe-SNAPSHOT
chisel
API
svsim
vcs
Backend
AssertGlobalMaxFailCount
AssertionSettings
BranchCoverageSettings
CompilationSettings
CompilationSettings
TraceSettings
TraceSettings
FsdbSettings
XProp
TMerge
XMerge
XProp
CoverageDirectory
CoverageName
CoverageSettings
Flag
Type
cm_seqnoconst
LicenseFile
Generic
Generic
Synopsys
Synopsys
Type
PlusSeparated
SimulationSettings
ToggleCoverageSettings
Backend
verilator
Backend
CompilationSettings
CompilationSettings
CoverageSettings
Parallelism
Different
Different
Type
Uniform
Uniform
Timing
TimingDisabled
TimingEnabled
Type
TraceKind
Fst
Type
Vcd
TraceStyle
Backend
Backend
Backend
Exceptions
FailedInitialization
HarnessCompilationFlags
Parameters
Parameters
Invocation
Settings
BackendSettingsModifications
BackendSettingsModifications
CommonCompilationSettings
CommonCompilationSettings
AvailableParallelism
Default
UpTo
AvailableParallelism
OptimizationStyle
Default
OptimizeForCompilationSpeed
OptimizeForSimulationSpeed
OptimizationStyle
Timescale
Timescale
Magnitude
Hundred
One
Ten
Type
Time
Type
Unit
Type
fs
ms
ns
ps
s
us
VerilogPreprocessorDefine
VerilogPreprocessorDefine
CommonSettingsModifications
CommonSettingsModifications
CommonSimulationSettings
CommonSimulationSettings
ModuleInfo
ModuleInfo
Port
PlusArg
Simulation
Simulation
Command
Done
GetBits
Log
Run
SetBits
Tick
Trace
Command
Controller
Message
Ack
Bits
Error
Log
Ready
Message
Port
UnexpectedEndOfMessages
Value
Workspace
Workspace
logger
phases
Checks
ClassLogLevelAnnotation
ClassLogLevelAnnotation
LazyLogging
LogClassNamesAnnotation
LogFileAnnotation
LogFileAnnotation
LogLevel
LogLevelAnnotation
LogLevelAnnotation
Logger
OutputCaptor
Logger
LoggerException
LoggerOption
LoggerOptions
LoggerOptionsView
firrtl
annotations
Annotation
Annotation
AnnotationClassNotFoundException
AnnotationException
AnnotationFileNotFoundException
AnnotationUtils
CompleteTarget
ComponentName
GenericTarget
HasSerializationHints
HasSerializationOverrides
InstanceTarget
InvalidAnnotationFileException
InvalidAnnotationJSONException
IsComponent
IsMember
IsModule
JsonProtocol
CompleteTargetSerializer
ComponentNameSerializer
GenericTargetSerializer
InstanceTargetSerializer
IsMemberSerializer
IsModuleSerializer
LoadMemoryFileTypeSerializer
ModuleNameSerializer
ModuleTargetSerializer
NamedSerializer
ReferenceTargetSerializer
TargetSerializer
UnrecognizedAnnotationSerializer
LoadMemoryAnnotation
MemoryFileInlineAnnotation
MemoryInitAnnotation
MemoryLoadFileType
MemoryLoadFileType
Binary
Hex
ModuleName
ModuleTarget
Named
NoTargetAnnotation
OverrideSerializationClass
ReferenceTarget
SingleTargetAnnotation
Target
Target
NamedException
TargetToken
TargetToken
Field
Index
Instance
OfModule
Ref
fromDefInstanceToTargetToken
fromDefModuleToTargetToken
fromIntToTargetToken
fromStringToTargetToken
UnrecogizedAnnotationsException
UnrecognizedAnnotation
UnserializableAnnotationException
UnserializableAnnotationException
UnserializeableAnnotation
graph
CyclicException
DiGraph
DiGraph
MutableDiGraph
PathNotFoundException
ir
AggregateType
AliasType
AnalogType
AnyRefPropertyType
ArrayTestParam
AsyncResetType
Attach
Block
Block
BooleanPropertyLiteral
BooleanPropertyType
BundleType
Circuit
CircuitWithAnnos
ClassPropertyType
ClockType
Comment
Conditionally
Connect
ConstType
DefClass
DefInstance
DefInstance
DefInstanceChoice
DefMemory
DefModule
DefNode
DefObject
DefOption
DefOptionCase
DefRegister
DefRegisterWithReset
DefTypeAlias
DefWire
Default
Direction
DoPrim
Domain
DomainDefine
DomainType
DoubleParam
DoublePropertyLiteral
DoublePropertyType
DoubleTestParam
EmptyStmt
Expression
ExtModule
Field
FileInfo
FileInfo
FirrtlNode
Flip
Flush
Formal
Fprint
GroundType
GroundType
HasInfo
HasName
Info
Input
IntModule
IntParam
IntTestParam
IntWidth
IntWidth
IntegerAddOp
IntegerMulOp
IntegerPropertyLiteral
IntegerPropertyType
IntegerShlOp
IntegerShrOp
IntrinsicExpr
IntrinsicStmt
IsDeclaration
IsInvalid
Layer
LayerBlock
LayerConfig
LayerConfig
Extract
Inline
ListConcatOp
Literal
MapTestParam
Module
Mux
NoInfo
Orientation
Output
Param
PathPropertyLiteral
PathPropertyType
Port
PrimOp
Print
ProbeDefine
ProbeExpr
ProbeForce
ProbeForceInitial
ProbeRead
ProbeRelease
ProbeReleaseInitial
ProbeType
PropAssign
PropExpr
PropPrimOp
PropertyType
RWProbeExpr
RWProbeType
RawStringParam
ReadUnderWrite
Reference
ResetType
SIntLiteral
SIntLiteral
SIntType
SequencePropertyType
SequencePropertyValue
Serializer
Statement
Stop
StringLit
StringLit
StringParam
StringPropertyLiteral
StringPropertyType
StringTestParam
SubAccess
SubField
SubIndex
TestMarker
Formal
Kind
Simulation
TestMarker
TestParam
Type
UIntLiteral
UIntLiteral
UIntType
UnknownType
UnknownWidth
ValidIf
VectorType
Verification
Version
Width
options
phases
AddDefaults
Checks
GetIncludes
WriteOutputAnnotations
BareShell
BufferedCustomFileEmission
CustomFileEmission
Dependency
Dependency
DependencyAPI
DependencyManager
DependencyManagerException
DependencyManagerUtils
ASCIICharSet
CharSet
PrettyCharSet
DoNotTerminateOnExit
DuplicateHandling
ExceptOnError
ExitCode
ExitFailure
ExitSuccess
GeneralError
HasShellOptions
IdentityLike
InputAnnotationFileAnnotation
InputAnnotationFileAnnotation
OptionsException
OptionsHelpException
OptionsView
OutputAnnotationFileAnnotation
OutputAnnotationFileAnnotation
Phase
PhaseException
PhaseManager
PhaseManager
PhasePrerequisiteException
ProgramArgsAnnotation
ProgramArgsAnnotation
RegisteredLibrary
Shell
ShellOption
Stage
StageError
StageMain
StageOption
StageOptions
StageOptionsView
StageUtils
TargetDirAnnotation
TargetDirAnnotation
TransformLike
Translator
Unserializable
Viewer
passes
memlib
InputConfigFileName
OutputConfigFileName
PassCircuitName
PassConfigUtil
PassModuleName
PassOption
ReplSeqMemAnnotation
ReplSeqMemAnnotation
wiring
SinkAnnotation
SourceAnnotation
CheckTypes
InlineAnnotation
InlineAnnotation
MemPortUtils
createMask
stage
phases
AddDefaults
Checks
AllowUnrecognizedAnnotations
FirrtlCircuitAnnotation
FirrtlOption
FirrtlOptions
FirrtlOptionsView
InfoModeAnnotation
InfoModeAnnotation
OutputFileAnnotation
OutputFileAnnotation
transforms
BlackBoxHelperAnno
BlackBoxInlineAnno
BlackBoxNotFoundException
BlackBoxPathAnno
BlackBoxTargetDirAnno
DedupGroupAnnotation
DontTouchAnnotation
FlattenAnnotation
MustDeduplicateAnnotation
NoDedupAnnotation
AnnotationSeq
AnnotationSeq
AttributeAnnotation
CDefMPort
CDefMemory
EmittedAnnotation
EmittedBtor2Circuit
EmittedBtor2CircuitAnnotation
EmittedCircuit
EmittedCircuitAnnotation
EmittedComponent
EmittedFirrtlCircuit
EmittedFirrtlCircuitAnnotation
EmittedVerilogCircuit
EmittedVerilogCircuitAnnotation
FirrtlUserException
MInfer
MPortDir
MRead
MReadWrite
MWrite
Parser
AppendInfo
GenInfo
IgnoreInfo
InfoMode
UseInfo
PrimOps
Add
And
Andr
AsAsyncReset
AsClock
AsSInt
AsUInt
Bits
Cat
Cvt
Div
Dshl
Dshr
Eq
Geq
Gt
Head
Leq
Lt
Mul
Neg
Neq
Not
Or
Orr
Pad
Rem
Shl
Shr
Sub
Tail
UnsafeDomainCast
Xor
Xorr
RenameMap
CircularRenameException
IllegalRenameException
RenameTargetException
RenameMap
Utils
circt
stage
phases
AddImplicitOutputFile
CIRCT
Checks
CIRCTOption
CIRCTOptions
CIRCTOptionsView
CIRCTTarget
Btor2
CHIRRTL
FIRRTL
HW
SystemVerilog
Type
Verilog
CIRCTTargetAnnotation
CIRCTTargetAnnotation
CLI
ChiselMain
ChiselStage
ChiselStage
EmittedMLIR
FirtoolBinaryPath
FirtoolOption
FirtoolOption
PreserveAggregate
All
OneDimVec
Type
Vec
PreserveAggregate
ConventionAnnotation
Implicits
BooleanImplicits
OutputDirAnnotation
convention
outputDir
chisel3
choice
Case
Group
ModuleChoice
connectable
Alignment
Connectable
Connectable
ConnectableOpExtension
ConnectableAlignment
ConnectableDontCare
ConnectableOperators
ConnectableVecOperators
domain
Domain
Field
Boolean
Integer
String
Type
Type
domains
ClockDomain
experimental
conversions
dataview
DataProduct
DataProduct
DataView
DataView
DataViewable
InvalidViewException
LowPriorityDataProduct
PartialDataView
RecordUpcastable
hierarchy
core
Clone
Definition
Definition
DefinitionBaseModuleExtensions
Hierarchy
Hierarchy
HierarchyBaseModuleExtensions
HierarchyIsA
HierarchyProto
ImportDefinitionAnnotation
Instance
Instance
InstanceBaseModuleExtensions
IsClone
IsInstantiable
IsInstantiable
IsInstantiableExtensions
IsLookupable
Lookupable
Lookupable
SimpleLookupable
Proto
Underlying
InsideHierarchyLibraryExtension
InstantiableClone
Instantiate
LibraryHooks
inlinetest
ElaboratedTest
HasTests
SimulatedTest
TestChoice
All
Globs
Globs
Type
TestConfiguration
TestConfiguration
TestHarness
TestHarnessGenerator
TestHarnessGenerator
TestHarnessInterface
TestParameters
TestResult
Failure
Success
Type
AffectsChiselName
AffectsChiselPrefix
Analog
Analog
AnyTargetable
AnyTargetable
BaseModule
BaseModuleExtensions
BaseModule
BundleLiteralException
BundleLiterals
AddBundleLiteralConstructor
ChiselSubtypeOf
CloneModuleAsRecord
DeprecatedSourceInfo
DoubleParam
ExtModule
HWTuple10
HWTuple2
HWTuple3
HWTuple4
HWTuple5
HWTuple6
HWTuple7
HWTuple8
HWTuple9
HasAutoTypename
HasTypeAlias
IntParam
IntrinsicModule
Markers
NoSourceInfo
OpaqueType
Param
PrintableParam
RawParam
RecordAlias
RecordAlias
SourceInfo
SourceInfo
SourceLine
StringParam
Targetable
Targetable
TargetableSyntax
Trace
UnlocatableSourceInfo
VecLiteralException
VecLiterals
AddObjectLiteralConstructor
AddVecLiteralConstructor
annotate
attach
AttachException
dedupGroup
doNotDedup
firrtlComment
flattenInstance
flattenInstanceAllowDedup
inlineInstance
inlineInstanceAllowDedup
noPrefix
prefix
requireIsAnnotatable
requireIsChiselType
requireIsHardware
skipPrefix
layers
HasTemporalInlineLayer
Temporal
Verification
Assert
Assume
Cover
ltl
AssertProperty
AssertPropertyLike
AssumeProperty
CoverProperty
Delay
EnsureProperty
Property
Property
RequireProperty
Sequence
Sequence
BoolSequence
SequenceAtom
naming
HasCustomIdentifier
IdentifierProposer
probe
Probe
ProbeValue
RWProbe
RWProbeValue
properties
AnyClassType
AnyClassType
Class
Class
ClassDefinitionOps
ClassInstanceOps
ClassType
Type
Type
ClassType
DynamicObject
DynamicObject
Path
Path
Property
ClassType
Property
ClassTypePropertyOps
PropertyArithmeticOps
PropertyArithmeticOps
PropertySequenceOps
PropertySequenceOps
PropertyType
reflect
DataMirror
HasMatchingZipOfChildren
internal
simulator
scalatest
Cli
ChiselOpts
EmitFsdb
EmitVcd
EmitVpd
FirtoolOpts
Scale
Simulator
HasCliOptions
CliOption
CliOption
HasCliOptions
stimulus
InlineTestStimulus
InlineTestStimulus
ResetProcedure
ResetProcedure
RunUntilFinished
RunUntilFinished
RunUntilSuccess
RunUntilSuccess
SimulationTestStimulus
SimulationTestStimulus
Stimulus
AnySimulatedModule
AnyTestableData
ChiselOptionsModifications
ChiselOptionsModifications
ChiselSim
ChiselSimulation
ChiselWorkspace
GeneratedWorkspaceInfo
ControlAPI
ElaboratedModule
EphemeralSimulator
Exceptions
AssertionFailed
TestFailed
TestsFailed
Timeout
FailedExpectationException
FailedExpectationException
FirtoolOptionsModifications
FirtoolOptionsModifications
HasSimulator
HasSimulator
simulators
LayerControl
Disable
Enable
EnableAll
Type
MacroText
NotSignal
Signal
Type
PeekPokable
PeekPokeAPI
TestableBool
TestableClock
TestableData
TestableEnum
TestableRecord
TestableReset
TestableSInt
TestableUInt
TestableVec
PeekPokeAPI
PeekPokeApiException
Peekable
Pokable
Randomization
Randomization
Settings
Settings
SimulatedModule
SimulationOutcome
Assertion
Failure
SignaledFailure
Success
Timeout
Type
Simulator
BackendInvocationDigest
BackendInvocationOutcome
CompilationFailed
SimulationDigest
Simulator
SimulatorAPI
TestableAggregate
TestableElement
UninitializedElementException
stage
phases
AddDedupGroupAnnotations
AddImplicitOutputAnnotationFile
AddImplicitOutputFile
AddSerializationAnnotations
Checks
Convert
Elaborate
Emitter
ChiselCircuitAnnotation
ChiselCircuitAnnotation
ChiselGeneratorAnnotation
ChiselGeneratorAnnotation
ChiselOption
ChiselOptions
ChiselOptionsView
ChiselOutputFileAnnotation
ChiselOutputFileAnnotation
CircuitSerializationAnnotation
FirrtlFileFormat
Format
CircuitSerializationAnnotation
DesignAnnotation
IncludeInlineTestsForModule
IncludeInlineTestsForModuleAnnotation
IncludeInlineTestsWithName
IncludeInlineTestsWithNameAnnotation
IncludeUtilMetadata
PrintFullStackTraceAnnotation
RemapLayer
RemapLayer
SourceRootAnnotation
SourceRootAnnotation
SuppressSourceInfoAnnotation
ThrowOnFirstErrorAnnotation
UseLegacyWidthBehavior
UseSRAMBlackbox
WarningConfigurationAnnotation
WarningConfigurationAnnotation
WarningConfigurationFileAnnotation
WarningConfigurationFileAnnotation
WarningsAsErrorsAnnotation
test
AllUnitTests
UnitTest
testing
scalatest
FileCheck
HasConfigMap
TestingDirectory
FileCheck
Exceptions
NonZeroExitCode
NotFound
FileCheck
StringHelpers
HasTestingDirectory
HasTestingDirectory
util
circt
dpi
DPIClockedVoidFunctionImport
DPIFunctionImport
DPINonVoidFunctionImport
RawClockedNonVoidFunctionCall
RawClockedVoidFunctionCall
RawUnclockedNonVoidFunctionCall
ClockGate
IsX
Mux2Cell
Mux4Cell
PlusArgsRetBundle
PlusArgsTest
PlusArgsValue
SizeOf
experimental
decode
BoolDecodeField
DecodeBundle
DecodeField
DecodePattern
DecodeTable
DecodeTableAnnotation
EspressoMinimizer
EspressoNotFoundException
Minimizer
QMCMinimizer
TruthTable
TruthTable
decoder
AutoBlackBox
AutoBundleFromVerilog
BitSet
BitSet
BoringUtils
BoringUtilsException
CIRCTSRAM
CIRCTSRAMInterface
CIRCTSRAMParameter
CIRCTSRAMParameter
CIRCTSRAMReadPort
CIRCTSRAMReadWritePort
CIRCTSRAMWritePort
FlattenInstance
FlattenInstanceAllowDedup
ForceNameAnnotation
InlineInstance
InlineInstanceAllowDedup
SlangUtils
forceName
getAnnotations
loadMemoryFromFile
loadMemoryFromFileInline
random
FibonacciLFSR
FibonacciLFSR
GaloisLFSR
GaloisLFSR
LFSR
LFSR
LFSRReduce
MaxPeriodFibonacciLFSR
MaxPeriodGaloisLFSR
PRNG
PRNG
PRNGIO
XNOR
XOR
Arbiter
ArbiterIO
BinaryToGray
BitPat
BitPat
Cat
Counter
Counter
Decoupled
DecoupledIO
DeqIO
EnqIO
Enum
Enum
Fill
FillInterleaved
GrayToBinary
HasBlackBoxInline
HasBlackBoxPath
HasBlackBoxResource
HasExtModuleInline
HasExtModulePath
HasExtModuleResource
ImplicitConversions
Irrevocable
IrrevocableIO
ListLookup
LockingArbiter
LockingArbiterLike
LockingRRArbiter
Log2
Lookup
MixedVec
MixedVec
MixedVecInit
Mux1H
MuxCase
MuxLookup
OHToUInt
Pipe
Pipe
PipeIO
PopCount
PriorityEncoder
PriorityEncoderOH
PriorityMux
Queue
Queue
ShadowFactory
QueueIO
RRArbiter
ReadyValidIO
ReadyValidIO
AddMethodsToReadyValid
RegEnable
Reverse
ShiftRegister
ShiftRegisters
SparseVec
SparseVec
DefaultValueBehavior
DynamicIndexEquivalent
Indeterminate
Type
UserSpecified
Lookup
Binary
Decoder
IfElse
OneHot
Type
OutOfBoundsBehavior
First
Indeterminate
Type
SwitchContext
UIntToOH
Valid
Valid
addAttribute
is
isPow2
log2Ceil
log2Down
log2Floor
log2Up
pla
scanLeftOr
scanRightOr
signedBitLength
simpleClassName
switch
unsignedBitLength
ActualDirection
ActualDirection
Bidirectional
Bidirectional
BidirectionalDirection
Default
Empty
Flipped
Input
Output
Unspecified
Aggregate
AliasedAggregateFieldException
ArrayTestParam
AsyncReset
AsyncReset
AutoClonetypeException
BiConnectException
Binary
BindingException
Bits
Bits
BlackBox
Bool
Bool
BoolFactory
BuildInfo
Bundle
Character
ChiselEnum
Type
Type
ChiselException
Clock
Clock
Const
Data
Data
AsReadOnly
ConnectableDefault
ConnectableVecDefault
DataEquality
Decimal
Disable
Disable
BeforeReset
Never
Type
DontCare
DoubleTestParam
ElaboratedCircuit
ElaboratedCircuit
Element
EnumType
ExpectedAnnotatableException
ExpectedChiselTypeException
ExpectedHardwareException
FirrtlFormat
FirrtlFormat
FormatWidth
Automatic
Fixed
Minimum
FormatWidth
FixedIOBaseModule
FixedIOExtModule
FixedIOModule
FixedIORawModule
FlatIO
Flipped
FormalContract
FormalTest
FullName
HasCustomConnectable
HasTarget
HasTarget
Hexadecimal
HierarchicalModuleName
IO
IgnoreSeqInBundle
ImplicitClock
ImplicitReset
Input
InstanceId
IntTestParam
InternalErrorException
Intrinsic
IntrinsicExpr
KnownWidth
KnownWidth
MapTestParam
Mem
Mem
MemBase
MixedDirectionAggregateException
Module
ResetType
Asynchronous
Default
Synchronous
Type
Uninferred
Module
MonoConnectException
Mux
Name
Num
Num
NumObject
Output
PString
Percent
Printable
Printable
Extensions
PrintableHelper
Printables
Public
RawModule
RebindingException
Record
Reg
RegInit
RegNext
RequireAsyncReset
RequireSyncReset
Reset
Reset
ResetType
SInt
SInt
SIntFactory
SimLog
SimLog
SimulationTest
SimulationTestHarness
SimulationTestHarnessInterface
SimulationTime
SourceInfoDoc
SpecialFirrtlSubstitution
SpecifiedDirection
SpecifiedDirection
Flip
Input
Output
Unspecified
StringTestParam
SyncReadMem
SyncReadMem
TestParam
UInt
UInt
UIntFactory
UnitTests
UnknownWidth
Vec
Vec
VecFactory
VecInit
VecLike
VerifPrintMacrosDoc
VerifStmtMacrosCompat
assert
assume
cover
VerificationStatement
WhenContext
Width
Width
Wire
WireDefault
WireFactory
WireInit
assert
Assert
assume
Assume
chiselTypeOf
cover
Cover
dontTouch
emitVerilog
fromBigIntToLiteral
fromBooleanToLiteral
fromIntToLiteral
fromIntToWidth
fromLongToLiteral
fromStringToLiteral
getVerilogString
layer
ABI
FileInclude
PreprocessorDefine
Root
Type
BlockReturnHandler
BlockReturnHandler
Convention
Bind
Type
CustomOutputDir
DefaultOutputDir
ExpectedNotElideBlocks
Layer
Layer
LayerConfig
Extract
Inline
LayerConfig
NoOutputDir
OutputDirBehavior
noModulePrefix
printf
Printf
stop
Stop
suppressEnumCastWarning
when
withClock
withClockAndReset
withDisable
withModulePrefix
withReset
withoutIO
chisel
/
chisel3
/
chisel3.experimental
/
Markers
Markers
chisel3.experimental.Markers
trait
Markers
Attributes
Source
HierarchyMarker.scala
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class
Object
trait
Matchable
class
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Attributes