ShiftRegister
Attributes
- Source
- Reg.scala
- Graph
-
- Supertypes
-
class Objecttrait Matchableclass Any
- Self type
-
ShiftRegister.type
Members list
Value members
Inherited methods
Returns the n-cycle delayed version of the input signal with reset initialization.
Returns the n-cycle delayed version of the input signal with reset initialization.
Value parameters
- en
-
enable the shift
- in
-
input to delay
- n
-
number of cycles to delay
- resetData
-
reset value for each register in the shift
Attributes
- Example
-
val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena) - Inherited from:
- ShiftRegisterIntf (hidden)
- Source
- RegIntf.scala
Returns the n-cycle delayed version of the input signal.
Returns the n-cycle delayed version of the input signal.
Enable is assumed to be true.
Value parameters
- in
-
input to delay
- n
-
number of cycles to delay
Attributes
- Example
-
val regDelayTwo = ShiftRegister(nextVal, 2) - Inherited from:
- ShiftRegisterIntf (hidden)
- Source
- RegIntf.scala
Returns the n-cycle delayed version of the input signal.
Returns the n-cycle delayed version of the input signal.
Value parameters
- en
-
enable the shift
- in
-
input to delay
- n
-
number of cycles to delay
Attributes
- Example
-
val regDelayTwo = ShiftRegister(nextVal, 2, ena) - Inherited from:
- ShiftRegisterIntf (hidden)
- Source
- RegIntf.scala
Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).
Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).
Value parameters
- en
-
enable the shift
- in
-
input to delay
- n
-
number of cycles to delay
- name
-
name of SyncReadMem object
- useDualPortSram
-
dual port or single port SRAM based implementation
Attributes
- Inherited from:
- ShiftRegisterIntf (hidden)
- Source
- RegIntf.scala