chisel
7.12.0+36-5ebc476b-SNAPSHOT
API
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chisel/chisel3/chisel3.util/SRAM

SRAM

chisel3.util.SRAM
object SRAM

Attributes

Source
SRAM.scala
Graph
Supertypes
class Object
trait Matchable
class Any
Self type
SRAM.type

Members list

Type members

Classlikes

implicit class SRAMDescriptionInstanceMethods(underlying: Instance[SRAMDescription])

Attributes

Source
SRAM.scala
Supertypes
class Object
trait Matchable
class Any

Value members

Concrete methods

def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

numReadPorts

The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

numReadwritePorts

The number of desired read/write ports >= 0, and the above two conditions must hold

numWritePorts

The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

size

The desired size of the inner SyncReadMem

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, readLatency: Int, writeLatency: Int)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

numReadPorts

The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

numReadwritePorts

The number of desired read/write ports >= 0, and the above two conditions must hold

numWritePorts

The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

readLatency

The number of cycles >= 1 between a read request and read response (applies to all ports)

size

The desired size of the inner SyncReadMem

writeLatency

The number of cycles >= 1 between a write request and read response (applies to all ports)

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

memoryFile

A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

numReadPorts

The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

numReadwritePorts

The number of desired read/write ports >= 0, and the above two conditions must hold

numWritePorts

The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

size

The desired size of the inner SyncReadMem

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

readPortClocks

A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

readwritePortClocks

A sequence of clocks for each read-write port; and the above two conditions must hold

size

The desired size of the inner SyncReadMem

writePortClocks

A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

memoryFile

A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

readPortClocks

A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

readwritePortClocks

A sequence of clocks for each read-write port; and the above two conditions must hold

size

The desired size of the inner SyncReadMem

writePortClocks

A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], readLatency: Int, writeLatency: Int, memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

memoryFile

A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

readLatency

The number of cycles >= 1 between a read request and read response (applies to all ports)

readPortClocks

A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

readwritePortClocks

A sequence of clocks for each read-write port; and the above two conditions must hold

size

The desired size of the inner SyncReadMem

writeLatency

The number of cycles >= 1 between a write request and read response (applies to all ports)

writePortClocks

A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

numReadPorts

The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

numReadwritePorts

The number of desired read/write ports >= 0, and the above two conditions must hold

numWritePorts

The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

size

The desired size of the inner SyncReadMem

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, readLatency: Int, writeLatency: Int)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

numReadPorts

The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

numReadwritePorts

The number of desired read/write ports >= 0, and the above two conditions must hold

numWritePorts

The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

readLatency

The number of cycles >= 1 between a read request and read response (applies to all ports)

size

The desired size of the inner SyncReadMem

writeLatency

The number of cycles >= 1 between a write request and read response (applies to all ports)

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

memoryFile

A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

numReadPorts

The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

numReadwritePorts

The number of desired read/write ports >= 0, and the above two conditions must hold

numWritePorts

The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

size

The desired size of the inner SyncReadMem

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, readLatency: Int, writeLatency: Int, memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

Type parameters

T

The data type of the memory element

Value parameters

memoryFile

A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

numReadPorts

The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

numReadwritePorts

The number of desired read/write ports >= 0, and the above two conditions must hold

numWritePorts

The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

readLatency

The number of cycles >= 1 between a read request and read response (applies to all ports)

size

The desired size of the inner SyncReadMem

writeLatency

The number of cycles >= 1 between a write request and read response (applies to all ports)

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Type parameters

T

The data type of the memory element

Value parameters

readPortClocks

A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

readwritePortClocks

A sequence of clocks for each read-write port; and the above two conditions must hold

size

The desired size of the inner SyncReadMem

writePortClocks

A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], readLatency: Int, writeLatency: Int)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Type parameters

T

The data type of the memory element

Value parameters

readLatency

The number of cycles >= 1 between a read request and read response (applies to all ports)

readPortClocks

A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

readwritePortClocks

A sequence of clocks for each read-write port; and the above two conditions must hold

size

The desired size of the inner SyncReadMem

writeLatency

The number of cycles >= 1 between a write request and read response (applies to all ports)

writePortClocks

A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Type parameters

T

The data type of the memory element

Value parameters

memoryFile

A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

readPortClocks

A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

readwritePortClocks

A sequence of clocks for each read-write port; and the above two conditions must hold

size

The desired size of the inner SyncReadMem

writePortClocks

A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala
def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], readLatency: Int, writeLatency: Int, memoryFile: MemoryFile)(implicit evidence: HasVecDataType[T], sourceInfo: SourceInfo): SRAMInterface[T]

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Generates a memory within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit Clock, rather than being given the implicit clock.

Type parameters

T

The data type of the memory element

Value parameters

memoryFile

A memory file whose path is emitted as Verilog directives to initialize the inner SyncReadMem

readLatency

The number of cycles >= 1 between a read request and read response (applies to all ports)

readPortClocks

A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

readwritePortClocks

A sequence of clocks for each read-write port; and the above two conditions must hold

size

The desired size of the inner SyncReadMem

writeLatency

The number of cycles >= 1 between a write request and read response (applies to all ports)

writePortClocks

A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

Attributes

Returns

A new SRAMInterface wire containing the control signals for each instantiated port

Throws
java.lang.IllegalArgumentException

if attempting to create a read-only memory (R >= 1, W === 0, RW === 0) or write-only memory (R === 0, W >= 1, RW === 0)

Note

The size of each Clock sequence determines the corresponding number of read, write, and read-write ports

This does not return the SyncReadMem itself, you must interact with it using the returned bundle

Source
SRAM.scala

Implicits

Implicits

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