chisel3.util.circt.Mux4Cell
Utility for constructing 4-to-1 MUX cell intrinsic. This intrinsic is lowered into verilog with vendor specic pragmas that guarantee utilization of 4-to-1 MUX cell in the synthesis process.
Attributes
Source
Synthesis.scala
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Supertypes
class Object
trait Matchable
class Any
Self type
Members list
Creates an intrinsic which will be lowered to a 4-to-1 MUX cell in synthesis tools.
Creates an intrinsic which will be lowered to a 4-to-1 MUX cell in synthesis tools.
Value parameters
sel
2-bit unsigned integer determining the input to choose.
v0
the value chosen when selector is 0
v1
the value chosen when selector is 1
v2
the value chosen when selector is 2
v3
the value chosen when selector is 3
Attributes
Example
Source
Synthesis.scala