loadMemoryFromFile
loadMemoryFromFile is an annotation generator that helps with loading a memory from a text file as a bind module. This relies on Verilator and Verilog's $readmemh or $readmemb.
This annotation, when a FIRRTL compiler runs will add Verilog directives to enable the specified memories to be initialized from files.
==Example module==
Consider a simple Module containing a memory:
import chisel3._
class UsesMem(memoryDepth: Int, memoryType: Data) extends Module {
val io = IO(new Bundle {
val address = Input(UInt(memoryType.getWidth.W))
val value = Output(memoryType)
})
val memory = Mem(memoryDepth, memoryType)
io.value := memory(io.address)
}
==Above module with annotation==
To load this memory from the file /workspace/workdir/mem1.hex.txt just add an import and annotate the memory:
import chisel3._
import chisel3.util.experimental.loadMemoryFromFile // <<-- new import here
class UsesMem(memoryDepth: Int, memoryType: Data) extends Module {
val io = IO(new Bundle {
val address = Input(UInt(memoryType.getWidth.W))
val value = Output(memoryType)
})
val memory = Mem(memoryDepth, memoryType)
io.value := memory(io.address)
loadMemoryFromFile(memory, "/workspace/workdir/mem1.hex.txt") // <<-- Note the annotation here
}
==Example file format==
A memory file should consist of ASCII text in either hex or binary format. The following example shows such a file formatted to use hex:
0
7
d
15
A binary file can be similarly constructed.
Attributes
- See also
-
https://github.com/freechipsproject/chisel3/tree/master/src/test/scala/chiselTests/LoadMemoryFromFileSpec.scala LoadMemoryFromFileSpec.scala in the test suite for additional examples.
Chisel3 Wiki entry on "Loading Memories in Simulation"
- Source
- LoadMemoryTransform.scala
- Graph
-
- Supertypes
-
class Objecttrait Matchableclass Any
- Self type
-
loadMemoryFromFile.type