chisel
7.9.0+2-5294dafe-SNAPSHOT
API
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chisel/chisel3/chisel3.simulator/ChiselWorkspace

ChiselWorkspace

chisel3.simulator.`package`.ChiselWorkspace
implicit class ChiselWorkspace(workspace: Workspace)

Attributes

Source
package.scala
Graph
Supertypes
class Object
trait Matchable
class Any

Members list

Type members

Classlikes

case class GeneratedWorkspaceInfo[T <: RawModule](dut: T, testHarnesses: Seq[ElaboratedTest[T]], outputAnnotations: AnnotationSeq)

Attributes

Source
package.scala
Supertypes
trait Serializable
trait Product
trait Equals
class Object
trait Matchable
class Any
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Value members

Concrete methods

def elaborateAndMakeTestHarnessWorkspaces[T <: RawModule & HasTests](generateModule: () => T, includeTestGlobs: Seq[String], args: Seq[String] = ..., firtoolArgs: Seq[String] = ...): Seq[(Workspace, ElaboratedTest[T], ElaboratedModule[RawModule & SimulationTestHarnessInterface])]

Attributes

Source
package.scala
def elaborateGeneratedModule[T <: RawModule](generateModule: () => T, args: Seq[String] = ..., firtoolArgs: Seq[String] = ...): ElaboratedModule[T]

Attributes

Source
package.scala
def generateWorkspaceSources[T <: RawModule](generateModule: () => T, args: Seq[String], firtoolArgs: Seq[String]): GeneratedWorkspaceInfo[T]

Use CIRCT to generate SystemVerilog sources, and potentially additional artifacts

Use CIRCT to generate SystemVerilog sources, and potentially additional artifacts

Attributes

Source
package.scala
def getModuleInfoPorts(dut: RawModule): Seq[(Data, Port)]

Attributes

Source
package.scala
def initializeModuleInfo(dut: RawModule, ports: Seq[Port]): Unit

Attributes

Source
package.scala
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