Pipe

chisel3.util.Pipe

See thePipe companion class

object Pipe

A factory to generate a hardware pipe. This can be used to delay Valid data by a design-time configurable number of cycles.

Here, we construct three different pipes using the different provided apply methods and hook them up together. The types are explicitly specified to show that these all communicate using Valid interfaces:

 val in: Valid[UInt]  = Wire(Valid(UInt(2.W)))

 /* A zero latency (combinational) pipe is connected to 'in' */
 val foo: Valid[UInt] = Pipe(in.valid, in.bits, 0)

 /* A one-cycle pipe is connected to the output of 'foo' */
 val bar: Valid[UInt] = Pipe(foo.valid, foo.bits)

 /* A two-cycle pipe is connected to the output of 'bar' */
 val baz: Valid[UInt] = Pipe(bar, 2)

Attributes

See also: Pipe class for an alternative API

Valid interface

Queue and the Queue factory for actual queues

The ShiftRegister factory to generate a pipe without a Valid interface
Companion: class
Source: Pipe.scala
Graph
Supertypes: class Object

trait Matchable

class Any
Self type: Pipe.type

Members list

Value members

Concrete methods

Generate a pipe from an explicit valid bit and some data

Value parameters

enqBits: the data (must be a hardware type)
enqValid: the valid bit (must be a hardware type)
latency: the number of pipeline stages

Attributes

Returns: the Valid output of the final pipeline stage
Source: Pipe.scala

Generate a one-stage pipe from an explicit valid bit and some data

Value parameters

enqBits: the data (must be a hardware type)
enqValid: the valid bit (must be a hardware type)

Attributes

Returns: the Valid output of the final pipeline stage
Source: Pipe.scala

Generate a pipe for a Valid interface

Value parameters

enq: a Valid interface (must be a hardware type)
latency: the number of pipeline stages

Attributes

Returns: the Valid output of the final pipeline stage
Source: Pipe.scala

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