Packages

c

chisel3

RawModule

abstract class RawModule extends BaseModule

Abstract base class for Modules that contain Chisel RTL. This abstract base class is a user-defined module which does not include implicit clock and reset and supports multiple IO() declarations.

Source
RawModule.scala
Linear Supertypes
BaseModule, HasId, internal.InstanceId, AnyRef, Any
Known Subclasses
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. RawModule
  2. BaseModule
  3. HasId
  4. InstanceId
  5. AnyRef
  6. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new RawModule()(implicit moduleCompileOptions: CompileOptions)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T

    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef must be a chisel type and not be bound to hardware.

    Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit

    Compatibility function.

    Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.

    Should NOT be used elsewhere. This API will NOT last.

    TODO: remove this, perhaps by removing Bindings checks in compatibility mode.

    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  10. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  11. val compileOptions: CompileOptions
  12. def desiredName: String

    Desired name of this module.

    Desired name of this module. Override this to give this module a custom, perhaps parametric, name.

    Definition Classes
    BaseModule
  13. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  14. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  15. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  16. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  17. def getCommands: Seq[Command]
    Attributes
    protected
  18. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  19. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  20. lazy val getPorts: Seq[Port]
  21. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  22. def instanceName: String

    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  23. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  24. final lazy val name: String

    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  25. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

    Called at the Module.apply(...) level after this Module has finished elaborating.

    Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.

    Helper method.

    Attributes
    protected
    Definition Classes
    BaseModule
  26. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  27. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  28. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  29. def parentModName: String
    Definition Classes
    HasId → InstanceId
  30. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  31. def pathName: String
    Definition Classes
    HasId → InstanceId
  32. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  33. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  34. def suggestName(name: ⇒ String): RawModule.this.type
    Definition Classes
    HasId
  35. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  36. final def toAbsoluteTarget: IsModule

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  37. def toString(): String
    Definition Classes
    AnyRef → Any
  38. final def toTarget: ModuleTarget

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  39. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  40. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  41. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()

Deprecated Value Members

  1. final def toNamed: ModuleName

    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModule → InstanceId
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2) toNamed API is deprecated -- use toTarget instead

    Note

    Should not be called until circuit elaboration is complete

Inherited from BaseModule

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped