Packages

sealed abstract class Bits extends Element with ToBoolable

A data type for values represented by a single bitvector. This provides basic bitwise operations.

Source
Bits.scala
Linear Supertypes
ToBoolable, Element, Data, SourceInfoDoc, NamedComponent, HasId, InstanceId, AnyRef, Any
Known Subclasses
Bool, SInt, UInt
Type Hierarchy
Ordering
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  2. Alphabetic
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Inherited
  1. Bits
  2. ToBoolable
  3. Element
  4. Data
  5. SourceInfoDoc
  6. NamedComponent
  7. HasId
  8. InstanceId
  9. AnyRef
  10. Any
Implicitly
  1. by DataEquality
  2. by toConnectableDefault
  3. by ConnectableDefault
  4. by any2stringadd
  5. by StringFormat
  6. by Ensuring
  7. by ArrowAssoc
  1. Hide All
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Visibility
  1. Public
  2. Protected

Abstract Value Members

  1. abstract def do_<<(that: UInt)(implicit sourceInfo: SourceInfo): Bits

  2. abstract def do_<<(that: Int)(implicit sourceInfo: SourceInfo): Bits

  3. abstract def do_<<(that: BigInt)(implicit sourceInfo: SourceInfo): Bits

  4. abstract def do_>>(that: UInt)(implicit sourceInfo: SourceInfo): Bits

  5. abstract def do_>>(that: Int)(implicit sourceInfo: SourceInfo): Bits

  6. abstract def do_>>(that: BigInt)(implicit sourceInfo: SourceInfo): Bits

  7. abstract def do_asSInt(implicit sourceInfo: SourceInfo): SInt

  8. abstract def do_unary_~(implicit sourceInfo: SourceInfo): Bits

Concrete Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final macro def ##(that: Bits): UInt

    Concatenation operator

    Concatenation operator

    that

    a hardware component

    returns

    this Bits concatenated to the most significant end of that

    Note

    The width of the returned Bits is width of this + width of that.

  3. final def ##: Int
    Definition Classes
    AnyRef → Any
  4. def +(other: String): String
    Implicit
    This member is added by an implicit conversion from Bits toany2stringadd[Bits] performed by method any2stringadd in scala.Predef.
    Definition Classes
    any2stringadd
  5. def ->[B](y: B): (Bits, B)
    Implicit
    This member is added by an implicit conversion from Bits toArrowAssoc[Bits] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @inline()
  6. final def :#=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    producer

    the right-hand-side of the connection, all members will be driving, none will be driven-to

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  7. final def :#=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    producer

    the right-hand-side of the connection, all members will be driving, none will be driven-to

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  8. final def :#=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  9. final def :<=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    producer

    the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  10. final def :<=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    producer

    the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  11. final def :<=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  12. final def :<>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    producer

    the right-hand-side of the connection

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  13. final def :<>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    producer

    the right-hand-side of the connection

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  14. final def :<>=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  15. final def :=(that: => Data)(implicit sourceInfo: SourceInfo): Unit

    The "strong connect" operator.

    The "strong connect" operator.

    For chisel3._, this operator is mono-directioned; all sub-elements of this will be driven by sub-elements of that.

    • Equivalent to this :#= that

    For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=

    • Equivalent to this :<>= that
    that

    the Data to connect from

    Definition Classes
    Data
  16. final def :>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    producer

    the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  17. final def :>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    producer

    the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")

    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  18. final def :>=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bits, S], sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    Implicit
    This member is added by an implicit conversion from Bits toConnectableDefault[Bits] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  19. final macro def <<(that: UInt): Bits

    Dynamic left shift operator

    Dynamic left shift operator

    that

    a hardware component

    returns

    this Bits dynamically shifted left by that many places, shifting in zeros from the right

    Note

    The width of the returned Bits is width of this + pow(2, width of that) - 1.

  20. final macro def <<(that: Int): Bits

    Static left shift operator

    Static left shift operator

    that

    an amount to shift by

    returns

    this Bits with that many zeros concatenated to its least significant end

    Note

    The width of the returned Bits is width of this + that.

  21. final macro def <<(that: BigInt): Bits

    Static left shift operator

    Static left shift operator

    that

    an amount to shift by

    returns

    this Bits with that many zeros concatenated to its least significant end

    Note

    The width of the returned Bits is width of this + that.

  22. final def <>(that: => Data)(implicit sourceInfo: SourceInfo): Unit

    The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

    The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

    For chisel3._, uses the chisel3.internal.BiConnect algorithm; sub-elements of that may end up driving sub-elements of this

    • Complicated semantics, hard to write quickly, will likely be deprecated in the future

    For Chisel._, emits the FIRRTL.<- operator

    • Equivalent to this :<>= that without the restrictions that bundle field names and vector sizes must match
    that

    the Data to connect from

    Definition Classes
    Data
  23. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  24. def ===(rhs: Bits): Bool

    Dynamic recursive equality operator for generic Data

    Dynamic recursive equality operator for generic Data

    rhs

    a hardware Data to compare lhs to

    returns

    a hardware Bool asserted if lhs is equal to rhs

    Implicit
    This member is added by an implicit conversion from Bits toDataEquality[Bits] performed by method DataEquality in chisel3.Data.
    Definition Classes
    DataEquality
    Exceptions thrown

    ChiselException when lhs and rhs are different types during elaboration time

  25. final macro def >>(that: UInt): Bits

    Dynamic right shift operator

    Dynamic right shift operator

    that

    a hardware component

    returns

    this Bits dynamically shifted right by the value of that component, inserting zeros into the most significant bits.

    Note

    The width of the returned Bits is unchanged, i.e., the width of this.

  26. final macro def >>(that: Int): Bits

    Static right shift operator

    Static right shift operator

    that

    an amount to shift by

    returns

    this Bits with that many least significant bits truncated

    Note

    The width of the returned Bits is unchanged, i.e., the width of this.

  27. final macro def >>(that: BigInt): Bits

    Static right shift operator

    Static right shift operator

    that

    an amount to shift by

    returns

    this Bits with that many least significant bits truncated

    Note

    The width of the returned Bits is unchanged, i.e., the width of this.

  28. final macro def apply(x: BigInt, y: BigInt): UInt

    Returns a subset of bits on this Bits from hi to lo (inclusive), statically addressed.

    Returns a subset of bits on this Bits from hi to lo (inclusive), statically addressed.

    x

    the high bit

    y

    the low bit

    returns

    a hardware component containing the requested bits

    Example:

    1. val myBits = "0b101".U
myBits(1, 0) // "0b01".U  // extracts the two least significant bits

// Note that zero-width ranges are also legal
myBits(-1, 0) // 0.U(0.W) // zero-width UInt
  29. final macro def apply(x: Int, y: Int): UInt

    Returns a subset of bits on this Bits from hi to lo (inclusive), statically addressed.

    Returns a subset of bits on this Bits from hi to lo (inclusive), statically addressed.

    x

    the high bit

    y

    the low bit

    returns

    a hardware component containing the requested bits

    Example:

    1. val myBits = "0b101".U
myBits(1, 0) // "0b01".U  // extracts the two least significant bits

// Note that zero-width ranges are also legal
myBits(-1, 0) // 0.U(0.W) // zero-width UInt
  30. final macro def apply(x: UInt): Bool

    Returns the specified bit on this wire as a Bool, dynamically addressed.

    Returns the specified bit on this wire as a Bool, dynamically addressed.

    x

    a hardware component whose value will be used for dynamic addressing

    returns

    the specified bit

  31. final macro def apply(x: Int): Bool

    Returns the specified bit on this Bits as a Bool, statically addressed.

    Returns the specified bit on this Bits as a Bool, statically addressed.

    x

    an index

    returns

    the specified bit

  32. final macro def apply(x: BigInt): Bool

    Returns the specified bit on this Bits as a Bool, statically addressed.

    Returns the specified bit on this Bits as a Bool, statically addressed.

    x

    an index

    returns

    the specified bit

  33. def as[S <: Data](implicit ev: <:<[Bits, S]): connectable.Connectable[S]

    Static cast to a super type

    Static cast to a super type

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  34. final macro def asBool: Bool

    Casts this Bits to a Bool

    Casts this Bits to a Bool

    Definition Classes
    ToBoolable
    Note

    The width must be known and equal to 1

  35. final macro def asBools: Seq[Bool]

    Returns the contents of this wire as a scala.collection.Seq of Bool.

  36. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  37. final macro def asSInt: SInt

    Reinterpret this Bits as an SInt

    Reinterpret this Bits as an SInt

    Note

    The arithmetic value is not preserved if the most-significant bit is set. For example, a UInt of width 3 and value 7 (0b111) would become an SInt of width 3 and value -1.

  38. macro def asTypeOf[T <: Data](that: T): T

    Does a reinterpret cast of the bits in this node into the format that provides.

    Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.

    x.asTypeOf(that) performs the inverse operation of x := that.toBits.

    Definition Classes
    Data
    Note

    bit widths are NOT checked, may pad or drop bits from input

    ,

    that should have known widths

  39. final macro def asUInt: UInt

    Reinterpret cast to UInt.

    Reinterpret cast to UInt.

    Definition Classes
    Data
    Note

    value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7

    ,

    Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.

  40. def autoSeed(name: String): Bits.this.type

    Takes the last seed suggested.

    Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).

    If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.

    Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.

    returns

    this object

    Definition Classes
    Data → HasId
  41. val base: Bits
    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  42. def binding: Option[Binding]
    Attributes
    protected[chisel3]
    Definition Classes
    Data
  43. def binding_=(target: Binding): Unit
    Attributes
    protected
    Definition Classes
    Data
  44. def circuitName: String
    Definition Classes
    HasId
  45. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native()
  46. def cloneType: Bits.this.type

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    cloneType must be defined for any Chisel object extending Data. It is responsible for constructing a basic copy of the object being cloned.

    returns

    a copy of the object.

    Definition Classes
    Bits → Data
  47. def containsAFlipped: Boolean
    Definition Classes
    Element → Data
  48. def do_##(that: Bits)(implicit sourceInfo: SourceInfo): UInt

  49. final def do_apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo): UInt

  50. final def do_apply(x: Int, y: Int)(implicit sourceInfo: SourceInfo): UInt

  51. final def do_apply(x: UInt)(implicit sourceInfo: SourceInfo): Bool

  52. final def do_apply(x: Int)(implicit sourceInfo: SourceInfo): Bool

  53. final def do_apply(x: BigInt)(implicit sourceInfo: SourceInfo): Bool

  54. def do_asBool(implicit sourceInfo: SourceInfo): Bool

    Definition Classes
    Bits → ToBoolable
  55. def do_asBools(implicit sourceInfo: SourceInfo): Seq[Bool]

  56. def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo): T

    Definition Classes
    Data
  57. def do_asUInt(implicit sourceInfo: SourceInfo): UInt

    Definition Classes
    Data
  58. final def do_extract(x: UInt)(implicit sourceInfo: SourceInfo): Bool

  59. final def do_extract(x: BigInt)(implicit sourceInfo: SourceInfo): Bool

  60. def do_head(n: Int)(implicit sourceInfo: SourceInfo): UInt

  61. def do_pad(that: Int)(implicit sourceInfo: SourceInfo): Bits.this.type

  62. def do_tail(n: Int)(implicit sourceInfo: SourceInfo): UInt

  63. final def do_take(n: Int)(implicit sourceInfo: SourceInfo): UInt
  64. def ensuring(cond: (Bits) => Boolean, msg: => Any): Bits
    Implicit
    This member is added by an implicit conversion from Bits toEnsuring[Bits] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  65. def ensuring(cond: (Bits) => Boolean): Bits
    Implicit
    This member is added by an implicit conversion from Bits toEnsuring[Bits] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  66. def ensuring(cond: Boolean, msg: => Any): Bits
    Implicit
    This member is added by an implicit conversion from Bits toEnsuring[Bits] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  67. def ensuring(cond: Boolean): Bits
    Implicit
    This member is added by an implicit conversion from Bits toEnsuring[Bits] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  68. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  69. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  70. def exclude(members: (Bits) => Data*): connectable.Connectable[Bits]

    Select members of base to exclude

    Select members of base to exclude

    members

    functions given the base return a member to exclude

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  71. def exclude: connectable.Connectable[Bits]

    Adds base to excludes

    Adds base to excludes

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  72. def excludeAs[S <: Data](members: (Bits) => Data*)(implicit ev: <:<[Bits, S]): connectable.Connectable[S]

    Select members of base to exclude and static cast to a new type

    Select members of base to exclude and static cast to a new type

    members

    functions given the base return a member to exclude

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  73. def excludeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[Bits, S]): connectable.Connectable[S]

    Programmatically select members of base to exclude and static cast to a new type

    Programmatically select members of base to exclude and static cast to a new type

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  74. def excludeProbes: connectable.Connectable[Bits]

    Exclude probes

    Exclude probes

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  75. final macro def extract(x: UInt): Bool

    Returns the specified bit on this wire as a Bool, dynamically addressed.

    Returns the specified bit on this wire as a Bool, dynamically addressed.

    x

    a hardware component whose value will be used for dynamic addressing

    returns

    the specified bit

  76. final macro def extract(x: BigInt): Bool

    Returns the specified bit on this Bits as a Bool, statically addressed.

    Returns the specified bit on this Bits as a Bool, statically addressed.

    x

    an index

    returns

    the specified bit

  77. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable])
  78. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  79. final def getWidth: Int

    Returns the width, in bits, if currently known.

    Returns the width, in bits, if currently known.

    Definition Classes
    Data
  80. def hasSeed: Boolean

    returns

    Whether either autoName or suggestName has been called

    Definition Classes
    HasId
  81. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  82. final macro def head(n: Int): UInt

    Head operator

    Head operator

    n

    the number of bits to take

    returns

    The n most significant bits of this Bits

  83. def instanceName: String
    Definition Classes
    HasId → InstanceId
  84. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  85. def isLit: Boolean
    Definition Classes
    Data
  86. final def isWidthKnown: Boolean

    Returns whether the width is currently known.

    Returns whether the width is currently known.

    Definition Classes
    Data
  87. def litOption: Option[BigInt]

    If this is a literal that is representable as bits, returns the value as a BigInt.

    If this is a literal that is representable as bits, returns the value as a BigInt. If not a literal, or not representable as bits (for example, is or contains Analog), returns None.

    Definition Classes
    Element → Data
  88. def litValue: BigInt

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Definition Classes
    Data
  89. def name: String
    Definition Classes
    Element
  90. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  91. def notWaivedOrSqueezedOrExcluded: Boolean

    True if no members are waived or squeezed or excluded

    True if no members are waived or squeezed or excluded

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  92. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  93. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  94. final macro def pad(that: Int): Bits.this.type

    Pad operator

    Pad operator

    that

    the width to pad to

    returns

    this @coll zero padded up to width that. If that is less than the width of the original component, this method returns the original component.

    Note

    For SInts only, this will do sign extension.

  95. def parentModName: String
    Definition Classes
    HasId → InstanceId
  96. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  97. def pathName: String
    Definition Classes
    HasId → InstanceId
  98. def squeeze(members: (Bits) => Data*): connectable.Connectable[Bits]

    Select members of base to squeeze

    Select members of base to squeeze

    members

    functions given the base return a member to squeeze

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  99. def squeeze: connectable.Connectable[Bits]

    Adds base to squeezes

    Adds base to squeezes

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  100. def squeezeAll: connectable.Connectable[Bits]

    Squeeze all members of base

    Squeeze all members of base

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  101. def squeezeAllAs[S <: Data](implicit ev: <:<[Bits, S]): connectable.Connectable[S]

    Squeeze all members of base and upcast to super type

    Squeeze all members of base and upcast to super type

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  102. def squeezeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]]): connectable.Connectable[Bits]

    Programmatically select members of base to squeeze

    Programmatically select members of base to squeeze

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  103. def suggestName(seed: => String): Bits.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

    seed

    The seed for the name of this component

    returns

    this object

    Definition Classes
    HasId
  104. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  105. final macro def tail(n: Int): UInt

    Tail operator

    Tail operator

    n

    the number of bits to remove

    returns

    This Bits with the n most significant bits removed.

  106. final macro def take(n: Int): UInt

    Grab the bottom n bits.

    Grab the bottom n bits. Return 0.U(0.W) if n==0.

  107. final def toAbsoluteTarget: ReferenceTarget

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Definition Classes
    NamedComponent → InstanceId
  108. final def toNamed: ComponentName

    Returns a FIRRTL ComponentName that references this object

    Returns a FIRRTL ComponentName that references this object

    Definition Classes
    NamedComponent → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  109. final def toPrintable: Printable

    Default print as Decimal

    Default print as Decimal

    Definition Classes
    Bits → Data
  110. final def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    NamedComponent
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The NamedComponent must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  111. def toString(): String
    Definition Classes
    AnyRef → Any
  112. final def toTarget: ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object

    Returns a FIRRTL ReferenceTarget that references this object

    Definition Classes
    NamedComponent → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  113. def typeName: String

    A non-ambiguous name of this Bits instance for use in generated Verilog names Inserts the width directly after the typeName, e.g.

    A non-ambiguous name of this Bits instance for use in generated Verilog names Inserts the width directly after the typeName, e.g. UInt4, SInt1

    Definition Classes
    Bits → Data
  114. final macro def unary_~: Bits

    Bitwise inversion operator

    Bitwise inversion operator

    returns

    this Bits with each bit inverted

  115. def unsafe: connectable.Connectable[Data]

    Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members

    Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  116. final def validateShiftAmount(x: Int)(implicit sourceInfo: SourceInfo): Int
    Attributes
    protected
  117. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  118. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  119. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()
  120. def waive(members: (Bits) => Data*): connectable.Connectable[Bits]

    Select members of base to waive

    Select members of base to waive

    members

    functions given the base return a member to waive

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  121. def waiveAll: connectable.Connectable[Bits]

    Waive all members of base

    Waive all members of base

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  122. def waiveAllAs[S <: Data](implicit ev: <:<[Bits, S]): connectable.Connectable[S]

    Waive all members of base and static cast to a new type

    Waive all members of base and static cast to a new type

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  123. def waiveAs[S <: Data](members: (Bits) => Data*)(implicit ev: <:<[Bits, S]): connectable.Connectable[S]

    Select members of base to waive and static cast to a new type

    Select members of base to waive and static cast to a new type

    members

    functions given the base return a member to waive

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  124. def waiveEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[Bits, S]): connectable.Connectable[S]

    Programmatically select members of base to waive and static cast to a new type

    Programmatically select members of base to waive and static cast to a new type

    Implicit
    This member is added by an implicit conversion from Bits toConnectable[Bits] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  125. def widthKnown: Boolean
    Definition Classes
    Element
  126. final def widthOption: Option[Int]

    Returns Some(width) if the width is known, else None.

    Returns Some(width) if the width is known, else None.

    Definition Classes
    Data

Deprecated Value Members

  1. def formatted(fmtstr: String): String
    Implicit
    This member is added by an implicit conversion from Bits toStringFormat[Bits] performed by method StringFormat in scala.Predef.
    Definition Classes
    StringFormat
    Annotations
    @deprecated @inline()
    Deprecated

    (Since version 2.12.16) Use formatString.format(value) instead of value.formatted(formatString), or use the f"" string interpolator. In Java 15 and later, formatted resolves to the new method in String which has reversed parameters.

  2. def →[B](y: B): (Bits, B)
    Implicit
    This member is added by an implicit conversion from Bits toArrowAssoc[Bits] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @deprecated
    Deprecated

    (Since version 2.13.0) Use -> instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.

Inherited from ToBoolable

Inherited from Element

Inherited from Data

Inherited from SourceInfoDoc

Inherited from NamedComponent

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Inherited by implicit conversion DataEquality fromBits to DataEquality[Bits]

Inherited by implicit conversion toConnectableDefault fromBits to Connectable[Bits]

Inherited by implicit conversion ConnectableDefault fromBits to ConnectableDefault[Bits]

Inherited by implicit conversion any2stringadd fromBits to any2stringadd[Bits]

Inherited by implicit conversion StringFormat fromBits to StringFormat[Bits]

Inherited by implicit conversion Ensuring fromBits to Ensuring[Bits]

Inherited by implicit conversion ArrowAssoc fromBits to ArrowAssoc[Bits]

Bitwise

Bitwise hardware operators

connection

Ungrouped

SourceInfoTransformMacro

These internal methods are not part of the public-facing API!

The equivalent public-facing methods do not have the do_ prefix or have the same name. Use and look at the documentation for those. If you want left shift, use <<, not do_<<. If you want conversion to a Seq of Bools look at the asBools above, not the one below. Users can safely ignore every method in this group!

🐉🐉🐉 Here be dragons... 🐉🐉🐉

These do_X methods are used to enable both implicit passing of SourceInfo while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your designs, are converted to their "hidden", do_*, via macro transformations. Without using macros here, only one of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a chained apply as an explicit 'implicit' argument and will throw type errors.

The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method into a call to an internal, hidden do_* that takes an explicit SourceInfo by inserting an implicitly[SourceInfo] as the explicit argument.