chisel3

package chisel3

This package contains the main chisel3 API.

Source: package.scala

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Package Members

package aop
package choice
This package contains Chisel language definitions for describing configuration options and their accepted values.
package connectable
package experimental
Package for experimental features, which may have their API changed, be removed, etc.
Package for experimental features, which may have their API changed, be removed, etc.
Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.
package interface
package layers
This package contains common layer.Layers used by Chisel generators.
package ltl
package naming
package probe
package properties
The properties package includes functionality related to non-hardware data.
The properties package includes functionality related to non-hardware data.
This entire package is currently very experimental, so expect some rough edges and rapid API evolution.
package reflect
package simulator
package stage
package test
package testing
package util
The util package provides extensions to core chisel for common hardware components and utility functions

Type Members

sealed abstract class ActualDirection extends AnyRef
Resolved directions for both leaf and container nodes, only visible after a node is bound (since higher-level specifications like Input and Output can override directions).
sealed trait Aggregate extends Data
An abstract class for data types that solely consist of (are an aggregate of) other Data objects.
class AliasedAggregateFieldException extends ChiselException
case class ArrayTestParam(value: Seq[TestParam]) extends TestParam with Product with Serializable
sealed class AsyncReset extends Element with AsyncResetIntf with Reset
Data type representing asynchronous reset signals
Data type representing asynchronous reset signals
These signals are similar to Clocks in that they must be glitch-free for proper circuit operation. Regs defined with the implicit reset being an AsyncReset will be asychronously reset registers.
class AutoClonetypeException extends ChiselException
case class BiConnectException(message: String) extends ChiselException with Product with Serializable
case class Binary(bits: Bits, width: FormatWidth = FormatWidth.Automatic) extends FirrtlFormat with Product with Serializable
Format bits as Binary
class BindingException extends ChiselException
sealed abstract class Bits extends Element with BitsIntf

abstract class BlackBox extends BaseBlackBox

Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.

Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

Note: The parameters API is experimental and may change

sealed class Bool extends UInt with BoolIntf with Reset
A data type for booleans, defined as a single bit indicating true or false.
trait BoolFactory extends AnyRef

abstract class Bundle extends Record

Base class for data types defined as a bundle of other data types.

Usage: extend this class (either as an anonymous or named class) and define members variables of Data subtypes to be elements in the Bundle.

Example of an anonymous IO bundle

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(64.W))
    val out = Output(SInt(128.W))
  })
}

Or as a named class

class Packet extends Bundle {
  val header = UInt(16.W)
  val addr   = UInt(16.W)
  val data   = UInt(32.W)
}
class MyModule extends Module {
  val inPacket = IO(Input(new Packet))
  val outPacket = IO(Output(new Packet))
  val reg = Reg(new Packet)
  reg := inPacket
  outPacket := reg
}

The fields of a Bundle are stored in an ordered Map called "elements" in reverse order of definition

class MyBundle extends Bundle {
  val foo = UInt(8.W)
  val bar = UInt(8.W)
}
val wire = Wire(new MyBundle)
wire.elements // VectorMap("bar" -> wire.bar, "foo" -> wire.foo)

case class Character(bits: Bits) extends FirrtlFormat with Product with Serializable
Format bits as Character
abstract class ChiselEnum extends ChiselEnumIntf
class ChiselException extends Exception
sealed class Clock extends Element with ClockIntf
type Connectable[T <: Data] = chisel3.connectable.Connectable[T]
abstract class Data extends HasId with NamedComponent with DataIntf
This forms the root of the type system for wire data types.
This forms the root of the type system for wire data types. The data value must be representable as some number (need not be known at Chisel compile time) of bits, and must have methods to pack / unpack structured data to / from bits.
case class Decimal(bits: Bits, width: FormatWidth = FormatWidth.Automatic) extends FirrtlFormat with Product with Serializable
Format bits as Decimal
class Disable extends DisableIntf
API for handling disabling of simulation constructs
API for handling disabling of simulation constructs
Disables may be non-synthesizable so they can only be used for disabling simulation constructs
The default disable is the "hasBeenReset" of the currently in scope reset. It can be set by the user via the withDisable API
Users can access the current Disable with Module.disable
case class DoubleTestParam(value: Double) extends TestParam with Product with Serializable
sealed trait ElaboratedCircuit extends AnyRef
The result of running Chisel elaboration
The result of running Chisel elaboration
Provides limited APIs for inspection of the resulting circuit.
abstract class Element extends Data
Element is a leaf data type: it cannot contain other Data objects.
Element is a leaf data type: it cannot contain other Data objects. Example uses are for representing primitive data types, like integers and bits.
abstract class EnumType extends Element with EnumTypeIntf
case class ExpectedAnnotatableException(message: String) extends BindingException with Product with Serializable
A function expected annotatable hardware
case class ExpectedChiselTypeException(message: String) extends BindingException with Product with Serializable
A function expected a Chisel type but got a hardware object
case class ExpectedHardwareException(message: String) extends BindingException with Product with Serializable
A function expected a hardware object but got a Chisel type
sealed abstract class FirrtlFormat extends Printable
Superclass for Firrtl format specifiers for Bits
sealed trait FixedIOBaseModule[A <: Data] extends BaseModule
A module or external module whose IO is generated from a specific generator.
A module or external module whose IO is generated from a specific generator. This module may have no additional IO created other than what is specified by its ioGenerator abstract member.
Annotations
@instantiable()
class FixedIOExtModule[A <: Data] extends ExtModule with FixedIOBaseModule[A]
A Chisel blackbox whose IO is determined by an IO generator.
A Chisel blackbox whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.
class FixedIOModule[A <: Data] extends Module with FixedIOBaseModule[A]
A Chisel module whose IO (in addition to clock and reset) is determined by an IO generator.
A Chisel module whose IO (in addition to clock and reset) is determined by an IO generator. This module cannot have additional IO created by modules that extend it.
class FixedIORawModule[A <: Data] extends RawModule with FixedIOBaseModule[A]
A Chisel module whose IO is determined by an IO generator.
A Chisel module whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.
case class FullName(data: Data) extends Printable with Product with Serializable
Put full name within parent namespace (eg.
Put full name within parent namespace (eg. bundleName.field)
trait HasCustomConnectable extends AnyRef
Trait to indicate that a subclass of Data has a custom Connectable.
Trait to indicate that a subclass of Data has a custom Connectable.
Users can implement the customConnectable method, which receives a default Connectable, and is expected to use the methods on Connectable to customize it. For example, a Bundle could define this by using connectable.Connectable.exclude(members* to always exlude a specific member:
```
class MyBundle extends Bundle with HasCustomConnectable {
  val foo = Bool()
  val bar = Bool()

  override def customConnectable[T <: Data](base: Connectable[T]): Connectable[T] = {
    base.exclude(_ => bar)
  }
}
```
sealed trait HasTarget extends AnyRef
Exposes target information and suggestName functionality of a NamedComponent.
case class Hexadecimal(bits: Bits, width: FormatWidth = FormatWidth.Automatic) extends FirrtlFormat with Product with Serializable
Format bits as Hexidecimal
trait IgnoreSeqInBundle extends AnyRef
Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.
Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.
Used to avoid raising an error/exception when a Seq is a public member of the bundle. This is useful if we those public Seq fields in the Bundle are unrelated to hardware construction.

trait ImplicitClock extends AnyRef

Provides an implicit Clock for use _within_ the RawModule

Be careful to define the Clock value before trying to use it. Due to Scala initialization order, the actual val defining the Clock must occur before any uses of the implicit Clock.

Example:

class MyModule extends RawModule with ImplicitClock {
  // Define a Clock value, it need not be called "implicitClock"
  val clk = IO(Input(Clock()))
  // Implement the virtual method to tell Chisel about this Clock value
  // Note that though this is a def, the actual Clock is assigned to a val (clk above)
  override protected def implicitClock = clk
  // Now we have a Clock to use in this RawModule
  val reg = Reg(UInt(8.W))
}

trait ImplicitReset extends AnyRef

Provides an implicit Reset for use _within_ the RawModule

Be careful to define the Reset value before trying to use it. Due to Scala initialization order, the actual val defining the Reset object must occur before any uses of the implicit Reset.

Example:

class MyModule extends RawModule with ImplicitReset {
  // Define a Reset value, it need not be called "implicitReset"
  val rst = IO(Input(AsyncReset()))
  // Implement the virtual method to tell Chisel about this Reset value
  // Note that though this is a def, the actual Reset is assigned to a val (rst above)
  override protected def implicitReset = clk
  // Now we have a Reset to use in this RawModule
  // Registers also require a clock
  val clock = IO(Input(Clock()))
  val reg = withClock(clock)(RegInit(0.U)) // Combine with ImplicitClock to get rid of this withClock
}

case class IntTestParam(value: BigInt) extends TestParam with Product with Serializable
class InternalErrorException extends ChiselException
sealed case class KnownWidth extends Width with Product with Serializable
case class MapTestParam(value: Map[String, TestParam]) extends TestParam with Product with Serializable
sealed class Mem[T <: Data] extends MemBase[T]
A combinational/asynchronous-read, sequential/synchronous-write memory.
A combinational/asynchronous-read, sequential/synchronous-write memory.
Writes take effect on the rising clock edge after the request. Reads are combinational (requests will return data on the same cycle). Read-after-write hazards are not an issue.
Note
when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)
sealed abstract class MemBase[T <: Data] extends MemBaseIntf[T] with HasId with NamedComponent
case class MixedDirectionAggregateException(message: String) extends BindingException with Product with Serializable
An aggregate had a mix of specified and unspecified directionality children
abstract class Module extends RawModule with ImplicitClock with ImplicitReset
Abstract base class for Modules, which behave much like Verilog modules.
Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.
Note
Module instantiations must be wrapped in a Module() call.
case class MonoConnectException(message: String) extends ChiselException with Product with Serializable
case class Name(data: Data) extends Printable with Product with Serializable
Put innermost name (eg.
Put innermost name (eg. field of bundle)
trait Num[T <: Data] extends NumIntf[T]
Abstract trait defining operations available on numeric-like hardware data types.
Abstract trait defining operations available on numeric-like hardware data types.
T
the underlying type of the number
trait NumObject extends AnyRef
NumObject has a lot of convenience methods for converting between BigInts and Double and BigDecimal
case class PString(str: String) extends Printable with Product with Serializable
Wrapper for printing Scala Strings
sealed abstract class Printable extends AnyRef
Superclass of things that can be printed in the resulting circuit
Superclass of things that can be printed in the resulting circuit
Usually created using the custom string interpolator p"...". Printable string interpolation is similar to String interpolation in Scala For example:
```
printf(p"The value of wire = $wire\n")
```
This is equivalent to writing:
```
printf("The value of wire = %d\n", wire)
```
All Chisel data types have a method .toPrintable that gives a default pretty print that can be accessed via p"...". This works even for aggregate types, for example:
```
val myVec = VecInit(5.U, 10.U, 13.U)
printf(p"myVec = $myVec\n")
// myVec = Vec(5, 10, 13)

val myBundle = Wire(new Bundle {
  val foo = UInt()
  val bar = UInt()
})
myBundle.foo := 3.U
myBundle.bar := 11.U
printf(p"myBundle = $myBundle\n")
// myBundle = Bundle(a -> 3, b -> 11)
```
Users can override the default behavior of .toPrintable in custom Bundle and Record types.
implicit final class PrintableHelper extends AnyVal
Implicit for custom Printable string interpolator
case class Printables(pables: Iterable[Printable]) extends Printable with Product with Serializable
Annotations
@nowarn()
trait Public extends AnyRef
A trait that can be mixed into a Chisel module to indicate that a module has external users.
A trait that can be mixed into a Chisel module to indicate that a module has external users.
This will result in a public FIRRTL module being produced.
abstract class RawModule extends BaseModule
Abstract base class for Modules that contain Chisel RTL.
Abstract base class for Modules that contain Chisel RTL. This abstract base class is a user-defined module which does not include implicit clock and reset and supports multiple IO() declarations.
case class RebindingException(message: String) extends BindingException with Product with Serializable
Attempted to re-bind an already bound (directionality or hardware) object
abstract class Record extends Data with Aggregate
Base class for Aggregates based on key values pairs of String and Data
Base class for Aggregates based on key values pairs of String and Data
Record should only be extended by libraries and fairly sophisticated generators. RTL writers should use Bundle. See Record#elements for an example.
trait RequireAsyncReset extends Module
Enforce that the Module.reset be Asynchronous (AsyncReset)
trait RequireSyncReset extends Module
Enforce that the Module.reset be Synchronous (Bool)
sealed trait Reset extends Element with ResetIntf
final class ResetType extends Element with Reset with ResetTypeIntf
"Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool
"Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool
Note
This shares a common interface with AsyncReset and Bool but is not their actual super type due to Bool inheriting from abstract class UInt
sealed class SInt extends Bits with SIntIntf with Num[SInt]
A data type for signed integers, represented as a binary bitvector.
A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.
trait SIntFactory extends AnyRef

sealed trait SimLog extends SimLogIntf

A file or I/O device to print to in simulation

val log = SimLog.file("logfile.log")
log.printf(cf"in = $in%0d\n")

val stderr = SimLog.StdErr
stderr.printf(cf"in = $in%0d\n")

// SimLog filenames themselves can be Printable.
// Be careful to avoid uninitialized registers.
val idx = Wire(UInt(8.W))
val log2 = SimLog.file(cf"logfile_$idx%0d.log")
log2.printf(cf"in = $in%0d\n")

trait SourceInfoDoc extends AnyRef
Provides ScalaDoc information for "hidden" do_* methods
Provides ScalaDoc information for "hidden" do_* methods
Mix this into classes/objects that have do_* methods to get access to the shared SourceInfoTransformMacro ScalaDoc group and the lengthy groupdesc below.
sealed trait SpecialFirrtlSubstitution extends AnyRef
Printable with special representation in FIRRTL
Printable with special representation in FIRRTL
Note
The name of the singleton object exactly matches the FIRRTL value.
sealed abstract class SpecifiedDirection extends AnyRef
User-specified directions.
case class StringTestParam(value: String) extends TestParam with Product with Serializable
sealed class SyncReadMem[T <: Data] extends MemBase[T] with SyncReadMemIntf[T]
A sequential/synchronous-read, sequential/synchronous-write memory.
A sequential/synchronous-read, sequential/synchronous-write memory.
Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.
Note
when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)
sealed abstract class TestParam extends AnyRef
Parameters for test declarations.
sealed class UInt extends Bits with UIntIntf with Num[UInt]
A data type for unsigned integers, represented as a binary bitvector.
A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.
trait UIntFactory extends AnyRef
sealed class Vec[T <: Data] extends Data with Aggregate with VecIntf[T] with VecLike[T]
A vector (array) of Data elements.
A vector (array) of Data elements. Provides hardware versions of various collection transformation functions found in software array implementations.
Careful consideration should be given over the use of Vec vs Seq or some other Scala collection. In general Vec only needs to be used when there is a need to express the hardware collection in a Reg or IO Bundle or when access to elements of the array is indexed via a hardware signal.
Example of indexing into a Vec using a hardware address and where the Vec is defined in an IO Bundle
```
val io = IO(new Bundle {
  val in = Input(Vec(20, UInt(16.W)))
  val addr = Input(UInt(5.W))
  val out = Output(UInt(16.W))
})
io.out := io.in(io.addr)
```
T
type of elements
Note
when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
trait VecFactory extends SourceInfoDoc
trait VecLike[T <: Data] extends VecLikeImpl[T] with IndexedSeq[T] with HasId
A trait for Vecs containing common hardware generators for collection operations.
trait VerifPrintMacrosDoc extends AnyRef
Scaladoc information for internal verification statement macros that are used in objects assert, assume and cover.
abstract class VerificationStatement extends NamedComponent
Base class for all verification statements: Assert, Assume, Cover, Stop and Printf.
final class WhenContext extends AnyRef
A WhenContext may represent a when, and elsewhen, or an otherwise.
A WhenContext may represent a when, and elsewhen, or an otherwise. Since FIRRTL does not have an "elsif" statement, alternatives must be mapped to nested if-else statements inside the alternatives of the preceeding condition. In order to emit proper FIRRTL, it is necessary to keep track of the depth of nesting of the FIRRTL whens. Due to the "thin frontend" nature of Chisel3, it is not possible to know if a when or elsewhen has a succeeding elsewhen or otherwise; therefore, this information is added by preprocessing the command queue.
sealed abstract class Width extends AnyRef
trait WireFactory extends AnyRef
implicit class fromBigIntToLiteral extends AnyRef
These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.
Also provides .asBool to scala.Boolean and .asUInt to String
Note that, for stylistic reasons, one should avoid extracting immediately after this call using apply, ie. 0.asUInt(1)(0) due to potential for confusion (the 1 is a bit length and the 0 is a bit extraction position). Prefer storing the result and then extracting from it.
implicit class fromBooleanToLiteral extends AnyRef
implicit class fromIntToLiteral extends fromBigIntToLiteral
implicit class fromIntToWidth extends AnyRef
implicit class fromLongToLiteral extends fromBigIntToLiteral
implicit class fromStringToLiteral extends AnyRef

Deprecated Type Members

trait InstanceId extends AnyRef
Public API to access Node/Signal names.
Public API to access Node/Signal names. currently, the node's name, the full path name, and references to its parent Module and component. These are only valid once the design has been elaborated, and should not be used during its construction.
Annotations
@deprecated
Deprecated
(Since version Chisel 6.7.0) User-defined annotations are not supported in CIRCT, use Targetable if you must.

Value Members

val Connectable: chisel3.connectable.Connectable.type
final val deprecatedMFCMessage: String("this feature will not be supported as part of the migration to the MLIR-based FIRRTL Compiler (MFC). For more information about this migration, please see the Chisel ROADMAP.md.")
final val deprecatedPublicAPIMsg: String("APIs in chisel3.internal are not intended to be public")
def getDataElements(a: Aggregate): Seq[Element]
implicit def string2Printable(str: String): Printable
def withName[T](name: String)(nameMe: => T): T
Use Chisel's naming algorithm to name the returned value
Use Chisel's naming algorithm to name the returned value
This will name typical "nameable" things like Chisel Data, but only if the object is created in the thunk.
T
The type of the thing to be named
name
The name to use
nameMe
A thunk that returns the thing to be named
returns
The thing, possibly now named
def withNames[T <: Product](names: String*)(nameMe: => T): T
Use Chisel's naming algorithm to name values within the returned Product value
Use Chisel's naming algorithm to name values within the returned Product value
This will name typical "nameable" things like Chisel Data, but only for objects crated in the thunk.
T
The type of the thing to be named
names
The names to use corresponding to interesting fields of the Product, empty Strings means no name
nameMe
The scala.Product to be named
returns
The thing, with members possibly named
object ActualDirection
object AsyncReset
object Bits extends UIntFactory
object Bool extends BoolFactory
case object BuildInfo extends Product with Serializable
object Clock
object Const
Create a constant type in FIRRTL, which is guaranteed to take a single constant value.
object Data
object Disable
case object DontCare extends Element with ConnectableDocs with Product with Serializable
RHS (source) for Invalidate API.
RHS (source) for Invalidate API. Causes connection logic to emit a DefInvalid when connected to an output port (or wire).
object ElaboratedCircuit
object FirrtlFormat
object FlatIO
The same as IO except there is no prefix when given a Record or Bundle.
The same as IO except there is no prefix when given a Record or Bundle. For Element (UInt, etc.) or Vec types, this is the same as IO. It is also the same as IO for chisel3.probe.Probe types.
Example:
1. class MyBundle extends Bundle { val foo = Input(UInt(8.W)) val bar = Output(UInt(8.W)) } class MyModule extends Module { val io = FlatIO(new MyBundle) // input [7:0] foo, // output [7:0] bar }
object Flipped
object FormalContract extends FormalContract$Intf
Create a contract block.
Create a contract block.
Outside of verification uses, the arguments passed to the contract are simply returned as contract results. During formal verification, the contract may act as a cutpoint by returning symbolic values for its results and using the contract body as constraint.
Within the contract body, RequireProperty and EnsureProperty can be used to describe the pre and post-conditions of the contract. During formal verification, contracts can be used to divide large formal checks into smaller pieces by first asserting some local properties hold, and then assuming those properties hold in the context of the larger proof.
Example:
1. The following is a contract with no arguments.
  FormalContract { RequireProperty(a >= 1) EnsureProperty(a + a >= 2) }
  The following is a contract with a single argument. It expresses the fact that the hardware implementation (a << 3) + a is equivalent to a * 9. During formal verification, this contract is interpreted as: - assert((a << 3) + a === a * 9) as a proof that the contract holds. - assume(b === a * 9) on a new symbolic value b as a simplification of other proofs.
  val b = FormalContract((a << 3) + a) { b => EnsureProperty(b === a * 9) }
  The following is a contract with multiple arguments. It expresses the fact that a carry-save adder with p, q, and r as inputs reduces the number of sum terms from p + q + r to c + s but doesn't change the sum of the terms. During formal verification, this contract is interpreted as: - assert(c + s === p + q + r) as a proof that the carry-save adder indeed compresses the three terms down to only two terms which have the same sum. - assume(u + v === p + q + r) on new symbolic values u and v as a simplification of other proofs.
  val s = p ^ q ^ r val c = (p & q | (p ^ q) & r) << 1 val (u, v) = FormalContract(c, s) { case (u, v) => EnsureProperty(u + v === p + q + r) }
object FormalTest
object HasTarget
case object HierarchicalModuleName extends Printable with SpecialFirrtlSubstitution with Product with Serializable
Represents the hierarchical name in the Verilog (%m)
object IO
object Input
Input, Output, and Flipped are used to define the directions of Module IOs.
Input, Output, and Flipped are used to define the directions of Module IOs.
Note that they currently clone their source argument, including its bindings.
Thus, an error will be thrown if these are used on bound Data
object Intrinsic
object IntrinsicExpr
object KnownWidth extends Serializable
object Mem extends Mem$Intf
object Module extends Module$Intf
object Mux extends Mux$Intf
object Num extends NumObject
Convenience methods for converting between BigInts and Double and BigDecimal
object Output
case object Percent extends Printable with Product with Serializable
Represents escaped percents
object Printable
object PrintfMacrosCompat

object Reg

Utility for constructing hardware registers

The width of a Reg (inferred or not) is copied from the type template

val r0 = Reg(UInt()) // width is inferred
val r1 = Reg(UInt(8.W)) // width is set to 8

val r2 = Reg(Vec(4, UInt())) // width is inferred
val r3 = Reg(Vec(4, UInt(8.W))) // width of each element is set to 8

class MyBundle {
  val unknown = UInt()
  val known   = UInt(8.W)
}
val r4 = Reg(new MyBundle)
// Width of r4.unknown is inferred
// Width of r4.known is set to 8

object RegInit
Utility for constructing hardware registers with an initialization value.
Utility for constructing hardware registers with an initialization value.
The register is set to the initialization value when the current implicit reset is high
The two forms of RegInit differ in how the type and width of the resulting Reg are specified.
Single Argument
The single argument form uses the argument to specify both the type and reset value. For non-literal Bits, the width of the Reg will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:
1. Literal Bits initializer: width will be set to match
```
val r1 = RegInit(1.U) // width will be inferred to be 1
val r2 = RegInit(1.U(8.W)) // width is set to 8
```
2. Non-Literal Element initializer - width will be inferred
```
val x = Wire(UInt())
val y = Wire(UInt(8.W))
val r1 = RegInit(x) // width will be inferred
val r2 = RegInit(y) // width will be inferred
```
3. Aggregate initializer - width will be set to match the aggregate
```
class MyBundle extends Bundle {
  val unknown = UInt()
  val known   = UInt(8.W)
}
val w1 = Reg(new MyBundle)
val w2 = RegInit(w1)
// Width of w2.unknown is inferred
// Width of w2.known is set to 8
```
Double Argument
The double argument form allows the type of the Reg and the default connection to be specified independently.
The width inference semantics for RegInit with two arguments match those of Reg. The first argument to RegInit is the type template which defines the width of the Reg in exactly the same way as the only argument to Wire.
More explicitly, you can reason about RegInit with multiple arguments as if it were defined as:
```
def RegInit[T <: Data](t: T, init: T): T = {
  val x = Reg(t)
  x := init
  x
}
```
object RegNext
Utility for constructing one-cycle delayed versions of signals
Utility for constructing one-cycle delayed versions of signals
The width of a RegNext is not set based on the next or init connections for Element types. In the following example, the width of bar will not be set and will be inferred by the FIRRTL compiler.
```
val foo = Reg(UInt(4.W))         // width is 4
val bar = RegNext(foo)           // width is unset
```
If you desire an explicit width, do not use RegNext and instead use a register with a specified width:
```
val foo = Reg(UInt(4.W))         // width is 4
val bar = Reg(chiselTypeOf(foo)) // width is 4
bar := foo
```
Also note that a RegNext of a Bundle will have it's width set for Aggregate types.
```
class MyBundle extends Bundle {
  val x = UInt(4.W)
}
val foo = Wire(new MyBundle)     // the width of foo.x is 4
val bar = RegNext(foo)           // the width of bar.x is 4
```
object Reset
object SInt extends SIntFactory
object SimLog
case object SimulationTime extends Printable with SpecialFirrtlSubstitution with Product with Serializable
Represents the simulation time in the Verilog, similar to %t + $time
object SpecifiedDirection
object SyncReadMem extends SyncReadMem$Intf
object UInt extends UIntFactory
object UnitTests
Utility to discover and generate all unit tests in the classpath.
case object UnknownWidth extends Width with Product with Serializable
object Vec extends VecFactory
object VecInit extends VecInit$Intf
object VerifStmtMacrosCompat
object Width

object Wire extends WireFactory

Utility for constructing hardware wires

The width of a Wire (inferred or not) is copied from the type template

val w0 = Wire(UInt()) // width is inferred
val w1 = Wire(UInt(8.W)) // width is set to 8

val w2 = Wire(Vec(4, UInt())) // width is inferred
val w3 = Wire(Vec(4, UInt(8.W))) // width of each element is set to 8

class MyBundle {
  val unknown = UInt()
  val known   = UInt(8.W)
}
val w4 = Wire(new MyBundle)
// Width of w4.unknown is inferred
// Width of w4.known is set to 8

object WireDefault extends WireDefaultImpl
Utility for constructing hardware wires with a default connection
Utility for constructing hardware wires with a default connection
The two forms of WireDefault differ in how the type and width of the resulting Wire are specified.
Single Argument
The single argument form uses the argument to specify both the type and default connection. For non-literal Bits, the width of the Wire will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:
1. Literal Bits initializer: width will be set to match
```
val w1 = WireDefault(1.U) // width will be inferred to be 1
val w2 = WireDefault(1.U(8.W)) // width is set to 8
```
2. Non-Literal Element initializer - width will be inferred
```
val x = Wire(UInt())
val y = Wire(UInt(8.W))
val w1 = WireDefault(x) // width will be inferred
val w2 = WireDefault(y) // width will be inferred
```
3. Aggregate initializer - width will be set to match the aggregate
```
class MyBundle {
  val unknown = UInt()
  val known   = UInt(8.W)
}
val w1 = Wire(new MyBundle)
val w2 = WireDefault(w1)
// Width of w2.unknown is inferred
// Width of w2.known is set to 8
```
Double Argument
The double argument form allows the type of the Wire and the default connection to be specified independently.
The width inference semantics for WireDefault with two arguments match those of Wire. The first argument to WireDefault is the type template which defines the width of the Wire in exactly the same way as the only argument to Wire.
More explicitly, you can reason about WireDefault with multiple arguments as if it were defined as:
```
def WireDefault[T <: Data](t: T, init: T): T = {
  val x = Wire(t)
  x := init
  x
}
```
object WireInit extends WireDefaultImpl
Utility for constructing hardware wires with a default connection
Utility for constructing hardware wires with a default connection
Alias for WireDefault.
Note
The Init in WireInit refers to a "default" connection. This is in contrast to RegInit where the Init refers to a value on reset.
object assert extends Assert$Intf
object assume extends Assume$Intf
object chiselTypeOf
Returns the chisel type of a hardware object, allowing other hardware to be constructed from it.
object cover extends Cover$Impl
object dontTouch
Marks that a signal's leaves are an optimization barrier to Chisel and the FIRRTL compiler.
Marks that a signal's leaves are an optimization barrier to Chisel and the FIRRTL compiler. This has the effect of guaranteeing that a signal will not be removed.
Example:
1. class MyModule extends Module { val io = IO(new Bundle { val a = Input(UInt(32.W)) val b = Output(UInt(32.W)) }) io.b := io.a val dead = io.a +% 1.U // normally dead would be pruned by DCE dontTouch(dead) // Marking it as such will preserve it }
Note
Because this is an optimization barrier, constants will not be propagated through a signal's leaves marked as dontTouch.
object emitVerilog
object getVerilogString
object layer
This object contains Chisel language features for creating layers.
This object contains Chisel language features for creating layers. Layers are collections of hardware that are not always present in the circuit. Layers are intended to be used to hold verification or debug code.
object printf extends PrintfIntf
Prints a message in simulation
Prints a message in simulation
See apply methods for use
object stop

object suppressEnumCastWarning

Suppress enum cast warnings

Users should use <EnumType>.safe when possible.

This is primarily used for casting from UInt to a Bundle type that contains an Enum.

class MyBundle extends Bundle {
  val addr = UInt(8.W)
  val op = OpEnum()
}

// Since this is a cast to a Bundle, cannot use OpCode.safe
val bundle = suppressEnumCastWarning {
  someUInt.asTypeOf(new MyBundle)
}

object when
object withClock
object withClockAndReset
object withDisable
Creates a new Disable scope
object withModulePrefix
Creates a block under which any generator that gets run results in a module whose name is prepended with the given prefix.
object withReset
object withoutIO

Packages

Package structure

chisel3

package chisel3

Package Members

Type Members

Deprecated Type Members

Value Members

Single Argument

Double Argument

Single Argument

Double Argument

Inherited from AnyRef

Inherited from Any

Ungrouped

Packages

Package structure

chisel3

package chisel3

Package Members

Type Members

Deprecated Type Members

Value Members

Single Argument

Double Argument

Single Argument

Double Argument

Inherited from AnyRef

Inherited from Any

Ungrouped

chisel3