object RegNext
Utility for constructing one-cycle delayed versions of signals
The width of a RegNext is not set based on the next or init connections for Element types. In the
following example, the width of bar will not be set and will be inferred by the FIRRTL compiler.
val foo = Reg(UInt(4.W)) // width is 4 val bar = RegNext(foo) // width is unset
If you desire an explicit width, do not use RegNext and instead use a register with a specified width:
val foo = Reg(UInt(4.W)) // width is 4 val bar = Reg(chiselTypeOf(foo)) // width is 4 bar := foo
Also note that a RegNext of a Bundle will have it's width set for Aggregate types.
class MyBundle extends Bundle { val x = UInt(4.W) } val foo = Wire(new MyBundle) // the width of foo.x is 4 val bar = RegNext(foo) // the width of bar.x is 4
- Source
- Reg.scala
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- def apply[T <: Data](next: T, init: T)(implicit sourceInfo: SourceInfo): T
Returns a register with an unset width connected to the signal
nextand with the reset valueinit. - def apply[T <: Data](next: T)(implicit sourceInfo: SourceInfo): T
Returns a register with an unset width connected to the signal
nextand with no reset value. - final def asInstanceOf[T0]: T0
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.