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chisel3

experimental

package experimental

Package for experimental features, which may have their API changed, be removed, etc.

Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.

Source
package.scala
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Type Members

  1. final class Analog extends Element

    Data type for representing bidirectional bitvectors of a given width

    Data type for representing bidirectional bitvectors of a given width

    Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout) pins. There is currently no support for reading or writing of Analog types within Chisel code.

    Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no effect.

    Analog types are generally connected using the bidirectional attach mechanism, but also support limited bulkconnect <>. Analog types are only allowed to be bulk connected *once* in a given module. This is to prevent any surprising consequences of last connect semantics.

    Note

    This API is experimental and subject to change

  2. abstract class BaseModule extends HasId

    Abstract base class for Modules, an instantiable organizational unit for RTL.

  3. class BundleLiteralException extends ChiselException
  4. trait ChiselAnnotation extends AnyRef

    Interface for Annotations in Chisel

    Interface for Annotations in Chisel

    Defines a conversion to a corresponding FIRRTL Annotation

  5. type ChiselEnum = EnumFactory
  6. final case class ChiselLegacyAnnotation extends ChiselAnnotation with RunFirrtlTransform with Product with Serializable
  7. implicit final class ChiselRange extends AnyVal
  8. type ClonePorts = internal.BaseModule.ClonePorts

    A record containing the results of CloneModuleAsRecord The apply method is retrieves the element with the supplied name.

  9. type Direction = ActualDirection
  10. case class DoubleParam(value: Double) extends Param with Product with Serializable
  11. abstract class EnumFactory extends AnyRef
  12. abstract class EnumType extends Element
  13. abstract class ExtModule extends BaseBlackBox

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

    A variant of BlackBox, this has a more consistent naming scheme in allowing multiple top-level IO and does not drop the top prefix.

    Example:
    1. Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

      IBUFDS #(.DIFF_TERM("TRUE"),
               .IOSTANDARD("DEFAULT")) ibufds (
       .IB(ibufds_IB),
       .I(ibufds_I),
       .O(ibufds_O)
      );

      To instantiate it, a BlackBox can be used like following:

      import chisel3._
      import chisel3.experimental._
      
      // Example with Xilinx differential buffer IBUFDS
      class IBUFDS extends ExtModule(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                         "IOSTANDARD" -> "DEFAULT"
                           )) {
        val O = IO(Output(Clock()))
        val I = IO(Input(Clock()))
        val IB = IO(Input(Clock()))
      }
    Note

    The parameters API is experimental and may change

  14. sealed class FixedPoint extends Bits with Num[FixedPoint] with HasBinaryPoint

    A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point may be inferred.

    A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point may be inferred.

    IMPORTANT: The API provided here is experimental and may change in the future.

  15. trait HasBinaryPoint extends AnyRef

    Chisel types that have binary points support retrieving literal values as Double or BigDecimal

  16. case class IntParam(value: BigInt) extends Param with Product with Serializable
  17. sealed class Interval extends Bits with Num[Interval] with HasBinaryPoint

    A sealed class representing a fixed point number that has a range, an additional parameter that can determine a minimum and maximum supported value.

    A sealed class representing a fixed point number that has a range, an additional parameter that can determine a minimum and maximum supported value. The range can be used to reduce the required widths particularly in primitive operations with other Intervals, the canonical example being

    val one = 1.I
    val six = Seq.fill(6)(one).reduce(_ + _)

    A UInt computed in this way would require a Width binary point The width and binary point may be inferred.

    IMPORTANT: The API provided here is experimental and may change in the future.

  18. trait NoChiselNamePrefix extends AnyRef

    Do not name instances of this type in chiselName

    Do not name instances of this type in chiselName

    By default, chiselName will include val names of instances of annotated classes as a prefix in final naming. Mixing in this trait to a class, object, or anonymous class instances will exclude the val name from chiselName naming.

    Example:
    1. import chisel3._
      import chisel3.experimental.{chiselName, NoChiselNamePrefix}
      
      // Note that this is not a Module
      @chiselName
      class Counter(w: Int) {
        val myReg = RegInit(0.U(w.W))
        myReg := myReg + 1.U
      }
      
      @chiselName
      class MyModule extends Module {
        val io = IO(new Bundle {
          val out = Output(UInt(8.W))
        })
        // Name of myReg will be "counter0_myReg"
        val counter0 = new Counter(8)
        // Name of myReg will be "myReg"
        val counter1 = new Counter(8) with NoChiselNamePrefix
        io.out := counter0.myReg + counter1.myReg
      }
  19. sealed abstract class Param extends AnyRef

    Parameters for BlackBoxes

  20. sealed trait PrivateType extends AnyRef

    Use PrivateObject to force users to specify width and binaryPoint by name

  21. case class RawParam(value: String) extends Param with Product with Serializable

    Unquoted String

  22. trait RunFirrtlTransform extends ChiselAnnotation

    Mixin for ChiselAnnotation that instantiates an associated FIRRTL Transform when this Annotation is present during a run of Driver.execute.

    Mixin for ChiselAnnotation that instantiates an associated FIRRTL Transform when this Annotation is present during a run of Driver.execute. Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking FIRRTL.

  23. case class StringParam(value: String) extends Param with Product with Serializable
  24. macro class chiselName extends internal.naming.chiselName

    Experimental macro for naming Chisel hardware values

    Experimental macro for naming Chisel hardware values

    By default, Chisel uses reflection for naming which only works for public fields of Bundle and Module classes. Applying this macro annotation to a class or object enables Chisel to name any hardware values within the annotated class or object.

    Annotations
    @compileTimeOnly( ... )
    Example:
    1. import chisel3._
      import chisel3.experimental.chiselName
      
      @chiselName
      class MyModule extends Module {
        val io = IO(new Bundle {
          val in = Input(UInt(8.W))
          val out = Output(UInt(8.W))
        })
        def createReg(): Unit = {
          // @chiselName allows Chisel to name this Reg
          val myReg = RegInit(io.in)
          io.out := myReg
        }
        createReg()
      }
  25. macro class dump extends internal.naming.dump
    Annotations
    @compileTimeOnly( ... )
  26. macro class treedump extends internal.naming.treedump
    Annotations
    @compileTimeOnly( ... )

Value Members

  1. val Direction: ActualDirection.type
  2. implicit def fromBigIntToIntParam(x: BigInt): IntParam
  3. implicit def fromDoubleToDoubleParam(x: Double): DoubleParam
  4. implicit def fromIntToIntParam(x: Int): IntParam
  5. implicit def fromLongToIntParam(x: Long): IntParam
  6. implicit def fromStringToStringParam(x: String): StringParam
  7. val requireIsChiselType: internal.requireIsChiselType.type
  8. val requireIsHardware: internal.requireIsHardware.type
  9. object Analog

    Object that provides factory methods for Analog objects

    Object that provides factory methods for Analog objects

    Note

    This API is experimental and subject to change

  10. object BundleLiterals
  11. object CloneModuleAsRecord
  12. object DataMirror

    Experimental hardware construction reflection API

  13. object EnumAnnotations
  14. object FixedPoint extends NumObject

    Factory and convenience methods for the FixedPoint class IMPORTANT: The API provided here is experimental and may change in the future.

  15. object IO
  16. object Interval extends NumObject

    Factory and convenience methods for the Interval class IMPORTANT: The API provided here is experimental and may change in the future.

  17. object annotate
  18. object attach
  19. object doNotDedup

    Marks that a module to be ignored in Dedup Transform in Firrtl pass

    Marks that a module to be ignored in Dedup Transform in Firrtl pass

    Example:
    1.  def fullAdder(a: UInt, b: UInt, myName: String): UInt = {
         val m = Module(new Module {
           val io = IO(new Bundle {
             val a = Input(UInt(32.W))
             val b = Input(UInt(32.W))
             val out = Output(UInt(32.W))
           })
           override def desiredName = "adder_" + myNname
           io.out := io.a + io.b
         })
         doNotDedup(m)
         m.io.a := a
         m.io.b := b
         m.io.out
       }
      
      class AdderTester extends Module
       with ConstantPropagationTest {
       val io = IO(new Bundle {
         val a = Input(UInt(32.W))
         val b = Input(UInt(32.W))
         val out = Output(Vec(2, UInt(32.W)))
       })
      
       io.out(0) := fullAdder(io.a, io.b, "mod1")
       io.out(1) := fullAdder(io.a, io.b, "mod2")
      }
    Note

    Calling this on Data creates an annotation that Chisel emits to a separate annotations file. This file must be passed to FIRRTL independently of the .fir file. The execute methods in chisel3.Driver will pass the annotations to FIRRTL automatically.

Deprecated Value Members

  1. val withClock: chisel3.withClock.type
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2) Use the version in chisel3._

  2. val withClockAndReset: chisel3.withClockAndReset.type
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2) Use the version in chisel3._

  3. val withReset: chisel3.withReset.type
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2) Use the version in chisel3._

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