Packages

class FibonacciLFSR extends PRNG with LFSR

Fibonacci Linear Feedback Shift Register (LFSR) generator.

A Fibonacci LFSR can be generated by defining a width and a set of tap points (corresponding to a polynomial). An optional initial seed and a reduction operation (XOR, the default, or XNOR) can be used to augment the generated hardware. The resulting hardware has support for a run-time programmable seed (via PRNGIO.seed) and conditional increment (via PRNGIO.increment).

If the user specifies a seed, then a compile-time check is added that they are not initializing the LFSR to a state which will cause it to lock up. If the user does not set a seed, then the least significant bit of the state will be set or reset based on the choice of reduction operator.

In the example below, a 4-bit Fibonacci LFSR is constructed. Tap points are defined as four and three (using LFSR convention of indexing from one). This results in the hardware configuration shown in the diagram.

val lfsr4 = Module(new FibonacciLFSR(4, Set(4, 3))
//                 +---+
// +-------------->|XOR|-------------------------------------------------------+
// |               +---+                                                       |
// |   +-------+     ^     +-------+           +-------+           +-------+   |
// |   |       |     |     |       |           |       |           |       |   |
// +---+  x^4  |<----+-----|  x^3  |<----------|  x^2  |<----------|  x^1  |<--+
//     |       |           |       |           |       |           |       |
//     +-------+           +-------+           +-------+           +-------+

If you require a maximal period Fibonacci LFSR of a specific width, you can use MaxPeriodFibonacciLFSR. If you only require a pseudorandom UInt you can use the FibonacciLFSR companion object.

Source
FibonacciLFSR.scala
See also

https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Fibonacci_LFSRs

Linear Supertypes
LFSR, PRNG, Module, RawModule, BaseModule, IsInstantiable, HasId, internal.InstanceId, AnyRef, Any
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  1. FibonacciLFSR
  2. LFSR
  3. PRNG
  4. Module
  5. RawModule
  6. BaseModule
  7. IsInstantiable
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
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Instance Constructors

  1. new FibonacciLFSR(width: Int, taps: Set[Int], seed: Option[BigInt] = Some(1), reduction: LFSRReduce = XOR, step: Int = 1, updateSeed: Boolean = false)

    width

    the width of the LFSR

    taps

    a set of tap points to use when constructing the LFSR

    seed

    an initial value for internal LFSR state. If None, then the LFSR state LSB will be set to a known safe value on reset (to prevent lock up).

    reduction

    the reduction operation (either XOR or XNOR)

    step

    the number of state updates per cycle

    updateSeed

    if true, when loading the seed the state will be updated as if the seed were the current state, if false, the state will be set to the seed

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T

    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef must be a chisel type and not be bound to hardware.

    Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit

    Compatibility function.

    Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.

    Should NOT be used elsewhere. This API will NOT last.

    TODO: remove this, perhaps by removing Bindings checks in compatibility mode.

    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  10. final val clock: Clock
    Definition Classes
    Module
  11. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  12. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  13. def delta(s: Seq[Bool]): Seq[Bool]

    State update function

    State update function

    s

    input state

    returns

    the next state

    Definition Classes
    FibonacciLFSRPRNG
  14. def desiredName: String

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The name of a module approximates the behavior of the Java Reflection method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:

    - Anonymous modules will get an "_Anon" tag - Modules defined in functions will use their class name and not a numeric name

    Definition Classes
    BaseModule
    Note

    If you want a custom or parametric name, override this method.

  15. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  16. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  17. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  18. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  19. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  20. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  21. def hasSeed: Boolean

    returns

    Whether either autoName or suggestName has been called

    Definition Classes
    HasId
  22. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  23. def instanceName: String

    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  24. val io: PRNGIO
    Definition Classes
    PRNG
  25. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  26. final lazy val name: String

    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  27. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

    Called at the Module.apply(...) level after this Module has finished elaborating.

    Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.

    Helper method.

    Attributes
    protected
    Definition Classes
    BaseModule
  28. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  29. final def nextState(s: Seq[Bool]): Seq[Bool]

    The method that will be used to update the state of this PRNG

    The method that will be used to update the state of this PRNG

    s

    input state

    returns

    the next state after step applications of PRNG.delta

    Definition Classes
    PRNG
  30. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  31. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  32. def parentModName: String
    Definition Classes
    HasId → InstanceId
  33. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  34. def pathName: String
    Definition Classes
    HasId → InstanceId
  35. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  36. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  37. val reduction: LFSRReduce

    The binary reduction operation used by this LFSR, either XOR or XNOR.

    The binary reduction operation used by this LFSR, either XOR or XNOR. This has the effect of mandating what seed is invalid.

    Definition Classes
    FibonacciLFSRLFSR
  38. final val reset: Reset
    Definition Classes
    Module
  39. def resetValue: Vec[Bool]

    Allow implementations to override the reset value, e.g., if some bits should be don't-cares.

    Allow implementations to override the reset value, e.g., if some bits should be don't-cares.

    Attributes
    protected
    Definition Classes
    LFSRPRNG
  40. val seed: Option[BigInt]
    Definition Classes
    PRNG
  41. def suggestName(seed: ⇒ String): FibonacciLFSR.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

    seed

    The seed for the name of this component

    returns

    this object

    Definition Classes
    HasId
  42. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  43. final def toAbsoluteTarget: IsModule

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  44. final def toNamed: ModuleName

    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  45. def toString(): String
    Definition Classes
    AnyRef → Any
  46. final def toTarget: ModuleTarget

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  47. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  48. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  49. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  50. val width: Int
    Definition Classes
    PRNG

Deprecated Value Members

  1. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6

  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from LFSR

Inherited from PRNG

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

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