class FibonacciLFSR extends PRNG with LFSR
Fibonacci Linear Feedback Shift Register (LFSR) generator.
A Fibonacci LFSR can be generated by defining a width and a set of tap points (corresponding to a polynomial). An optional initial seed and a reduction operation (XOR, the default, or XNOR) can be used to augment the generated hardware. The resulting hardware has support for a run-time programmable seed (via PRNGIO.seed) and conditional increment (via PRNGIO.increment).
If the user specifies a seed, then a compile-time check is added that they are not initializing the LFSR to a state which will cause it to lock up. If the user does not set a seed, then the least significant bit of the state will be set or reset based on the choice of reduction operator.
In the example below, a 4-bit Fibonacci LFSR is constructed. Tap points are defined as four and three (using LFSR convention of indexing from one). This results in the hardware configuration shown in the diagram.
val lfsr4 = Module(new FibonacciLFSR(4, Set(4, 3)) // +---+ // +-------------->|XOR|-------------------------------------------------------+ // | +---+ | // | +-------+ ^ +-------+ +-------+ +-------+ | // | | | | | | | | | | | // +---+ x^4 |<----+-----| x^3 |<----------| x^2 |<----------| x^1 |<--+ // | | | | | | | | // +-------+ +-------+ +-------+ +-------+
If you require a maximal period Fibonacci LFSR of a specific width, you can use MaxPeriodFibonacciLFSR. If you only require a pseudorandom UInt you can use the FibonacciLFSR companion object.
- Source
- FibonacciLFSR.scala
- See also
https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Fibonacci_LFSRs
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new
FibonacciLFSR(width: Int, taps: Set[Int], seed: Option[BigInt] = Some(1), reduction: LFSRReduce = XOR, step: Int = 1, updateSeed: Boolean = false)
- width
the width of the LFSR
- taps
a set of tap points to use when constructing the LFSR
- seed
an initial value for internal LFSR state. If None, then the LFSR state LSB will be set to a known safe value on reset (to prevent lock up).
- reduction
- step
the number of state updates per cycle
- updateSeed
if true, when loading the seed the state will be updated as if the seed were the current state, if false, the state will be set to the seed
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def
IO[T <: Data](iodef: T): T
This must wrap the datatype used to set the io field of any Module.
This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])
Items in [] are optional.
The granted iodef must be a chisel type and not be bound to hardware.
Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.
TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.
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def
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Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
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def
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Compatibility function.
Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.
Should NOT be used elsewhere. This API will NOT last.
TODO: remove this, perhaps by removing Bindings checks in compatibility mode.
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asInstanceOf[T0]: T0
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def
circuitName: String
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val
clock: Clock
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def
delta(s: Seq[Bool]): Seq[Bool]
State update function
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def
desiredName: String
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The name of a module approximates the behavior of the Java Reflection method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:
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"_Anon"tag - Modules defined in functions will use their class name and not a numeric name- Definition Classes
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If you want a custom or parametric name, override this method.
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def
getModulePorts: Seq[Data]
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def
hasSeed: Boolean
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Whether either autoName or suggestName has been called
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def
hashCode(): Int
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def
instanceName: String
Signal name (for simulation).
Signal name (for simulation).
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val
io: PRNGIO
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final
def
isInstanceOf[T0]: Boolean
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lazy val
name: String
Legalized name of this module.
Legalized name of this module.
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def
nameIds(rootClass: Class[_]): HashMap[HasId, String]
Called at the Module.apply(...) level after this Module has finished elaborating.
Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.
Helper method.
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final
def
ne(arg0: AnyRef): Boolean
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final
def
nextState(s: Seq[Bool]): Seq[Bool]
The method that will be used to update the state of this PRNG
The method that will be used to update the state of this PRNG
- s
input state
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the next state after
stepapplications of PRNG.delta
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final
def
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def
parentModName: String
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def
parentPathName: String
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def
pathName: String
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def
portsContains(elem: Data): Boolean
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def
portsSize: Int
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val
reduction: LFSRReduce
The binary reduction operation used by this LFSR, either XOR or XNOR.
The binary reduction operation used by this LFSR, either XOR or XNOR. This has the effect of mandating what seed is invalid.
- Definition Classes
- FibonacciLFSR → LFSR
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final
val
reset: Reset
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def
resetValue: Vec[Bool]
Allow implementations to override the reset value, e.g., if some bits should be don't-cares.
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val
seed: Option[BigInt]
- Definition Classes
- PRNG
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def
suggestName(seed: ⇒ String): FibonacciLFSR.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
- seed
The seed for the name of this component
- returns
this object
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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final
def
toAbsoluteTarget: IsModule
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
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- BaseModule → InstanceId
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Should not be called until circuit elaboration is complete
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final
def
toNamed: ModuleName
Returns a FIRRTL ModuleName that references this object
Returns a FIRRTL ModuleName that references this object
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Should not be called until circuit elaboration is complete
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def
toString(): String
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final
def
toTarget: ModuleTarget
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
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Should not be called until circuit elaboration is complete
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def
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def
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final
def
wait(arg0: Long): Unit
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val
width: Int
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lazy val
getPorts: Seq[Port]
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(Since version Chisel 3.5) Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6
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def
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(Since version Chisel 3.5) Use withClock at Module instantiation
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def
override_reset: Option[Bool]
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def
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(Since version Chisel 3.5) Use withClock at Module instantiation
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