Packages

c

chisel3.util

RRArbiter

class RRArbiter[T <: Data] extends LockingRRArbiter[T]

Hardware module that is used to sequence n producers into 1 consumer. Producers are chosen in round robin order.

Annotations
@chiselName()
Source
Arbiter.scala
Example:
  1. val arb = Module(new RRArbiter(UInt(), 2))
    arb.io.in(0) <> producer0.io.out
    arb.io.in(1) <> producer1.io.out
    consumer.io.in <> arb.io.out
Linear Supertypes
LockingRRArbiter[T], LockingArbiterLike[T], LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, internal.InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. RRArbiter
  2. LockingRRArbiter
  3. LockingArbiterLike
  4. LegacyModule
  5. MultiIOModule
  6. RawModule
  7. BaseModule
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new RRArbiter(gen: T, n: Int)

    gen

    data type

    n

    number of inputs

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T

    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef must be a chisel type and not be bound to hardware.

    Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit

    Compatibility function.

    Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.

    Should NOT be used elsewhere. This API will NOT last.

    TODO: remove this, perhaps by removing Bindings checks in compatibility mode.

    Definition Classes
    BaseModule
  8. def _compatIoPortBound(): Boolean
    Attributes
    protected
    Definition Classes
    LegacyModule
  9. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  10. lazy val choice: UInt
    Definition Classes
    LockingRRArbiterLockingArbiterLike
  11. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  12. final val clock: Clock
    Definition Classes
    MultiIOModule
  13. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  14. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  15. def desiredName: String

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The name of a module approximates the behavior of the Java Reflection method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:

    - Anonymous modules will get an "_Anon" tag - Modules defined in functions will use their class name and not a numeric name

    Definition Classes
    BaseModule
    Note

    If you want a custom or parametric name, override this method.

  16. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  17. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  18. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  19. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  20. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  21. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  22. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  23. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
  24. def grant: Seq[Bool]
    Definition Classes
    LockingRRArbiterLockingArbiterLike
  25. lazy val grantMask: IndexedSeq[Bool]
    Definition Classes
    LockingRRArbiter
  26. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  27. def instanceName: String

    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  28. val io: ArbiterIO[T]
    Definition Classes
    LockingArbiterLike → LegacyModule
  29. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  30. lazy val lastGrant: UInt
    Definition Classes
    LockingRRArbiter
  31. final lazy val name: String

    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  32. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

    Called at the Module.apply(...) level after this Module has finished elaborating.

    Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.

    Helper method.

    Attributes
    protected
    Definition Classes
    BaseModule
  33. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  34. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  35. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  36. var override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    LegacyModule
  37. var override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    LegacyModule
  38. def parentModName: String
    Definition Classes
    HasId → InstanceId
  39. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  40. def pathName: String
    Definition Classes
    HasId → InstanceId
  41. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  42. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  43. final val reset: Reset
    Definition Classes
    MultiIOModule
  44. def suggestName(name: ⇒ String): RRArbiter.this.type
    Definition Classes
    HasId
  45. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  46. final def toAbsoluteTarget: IsModule

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  47. final def toNamed: ModuleName

    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  48. def toString(): String
    Definition Classes
    AnyRef → Any
  49. final def toTarget: ModuleTarget

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModule → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  50. lazy val validMask: IndexedSeq[Bool]
    Definition Classes
    LockingRRArbiter
  51. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  52. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  53. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()

Inherited from LockingRRArbiter[T]

Inherited from LockingArbiterLike[T]

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped