abstract class ReadyValidIO[+T <: Data] extends Bundle

An I/O Bundle containing 'valid' and 'ready' signals that handshake the transfer of data stored in the 'bits' subfield. The base protocol implied by the directionality is that the producer uses the interface as-is (outputs bits) while the consumer uses the flipped interface (inputs bits). The actual semantics of ready/valid are enforced via the use of concrete subclasses.

Source
Decoupled.scala
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  1. ReadyValidIO
  2. Bundle
  3. Record
  4. Aggregate
  5. Data
  6. SourceInfoDoc
  7. NamedComponent
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
Implicitly
  1. by AddMethodsToReadyValid
  2. by DataEquality
  3. by toConnectableDefault
  4. by ConnectableDefault
  5. by any2stringadd
  6. by StringFormat
  7. by Ensuring
  8. by ArrowAssoc
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  1. Public
  2. Protected

Instance Constructors

  1. new ReadyValidIO(gen: T)

    gen

    the type of data to be wrapped in Ready/Valid

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. def +(other: String): String
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toany2stringadd[ReadyValidIO[T]] performed by method any2stringadd in scala.Predef.
    Definition Classes
    any2stringadd
  4. def ->[B](y: B): (ReadyValidIO[T], B)
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toArrowAssoc[ReadyValidIO[T]] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @inline()
  5. final def :#=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    producer

    the right-hand-side of the connection, all members will be driving, none will be driven-to

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  6. final def :#=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    producer

    the right-hand-side of the connection, all members will be driving, none will be driven-to

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  7. final def :#=[S <: Data](lProducer: => S)(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  8. final def :<=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    producer

    the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  9. final def :<=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    producer

    the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  10. final def :<=[S <: Data](lProducer: => S)(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  11. final def :<>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    producer

    the right-hand-side of the connection

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  12. final def :<>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    producer

    the right-hand-side of the connection

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  13. final def :<>=[S <: Data](lProducer: => S)(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  14. final def :=(that: => Data)(implicit sourceInfo: SourceInfo): Unit

    The "strong connect" operator.

    The "strong connect" operator.

    For chisel3._, this operator is mono-directioned; all sub-elements of this will be driven by sub-elements of that.

    • Equivalent to this :#= that

    For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=

    • Equivalent to this :<>= that
    that

    the Data to connect from

    Definition Classes
    Data
  15. final def :>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    producer

    the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  16. final def :>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    producer

    the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  17. final def :>=[S <: Data](lProducer: => S)(implicit evidence: =:=[ReadyValidIO[T], S], sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectableDefault[ReadyValidIO[T]] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  18. final def <>(that: => Data)(implicit sourceInfo: SourceInfo): Unit

    The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

    The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

    For chisel3._, uses the chisel3.internal.BiConnect algorithm; sub-elements of that may end up driving sub-elements of this

    • Complicated semantics, hard to write quickly, will likely be deprecated in the future

    For Chisel._, emits the FIRRTL.<- operator

    • Equivalent to this :<>= that without the restrictions that bundle field names and vector sizes must match
    that

    the Data to connect from

    Definition Classes
    Data
  19. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  20. def ===(rhs: ReadyValidIO[T]): Bool

    Dynamic recursive equality operator for generic Data

    Dynamic recursive equality operator for generic Data

    rhs

    a hardware Data to compare lhs to

    returns

    a hardware Bool asserted if lhs is equal to rhs

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toDataEquality[ReadyValidIO[T]] performed by method DataEquality in chisel3.Data.
    Definition Classes
    DataEquality
    Exceptions thrown

    ChiselException when lhs and rhs are different types during elaboration time

  21. def _cloneTypeImpl: Record

    Implementation of cloneType that is [optionally for Record] overridden by the compiler plugin

    Implementation of cloneType that is [optionally for Record] overridden by the compiler plugin

    Attributes
    protected
    Definition Classes
    Record
    Note

    This should _never_ be overridden or called in user-code

  22. def _elementsImpl: Iterable[(String, Any)]

    This method is implemented by the compiler plugin

    This method is implemented by the compiler plugin

    Attributes
    protected
    Definition Classes
    Bundle
    Note

    For some reason, the Scala compiler errors on child classes if this method is made virtual. It appears that the way the plugin implements this method is insufficient for implementing virtual methods. It is probably better kept concrete for future refactoring.

  23. def _typeNameConParams: Iterable[Any]

    The list of parameter accessors used in the constructor of this chisel3.Record.

    The list of parameter accessors used in the constructor of this chisel3.Record.

    Attributes
    protected
    Definition Classes
    Record
    Note

    This is automatically overridden via the compiler plugin for user-defined bundles that mix-in chisel3.experimental.HasAutoTypename, and is meant for internal Chisel use only. Can not be manually overridden by users, or else an error will be thrown.

    ,

    This lives in Record rather than the chisel3.experimental.HasAutoTypename trait, due to compiler implementation details preventing us from overriding a definition within a trait via the compiler plugin

  24. def _usingPlugin: Boolean

    Indicates if a concrete Bundle class was compiled using the compiler plugin

    Indicates if a concrete Bundle class was compiled using the compiler plugin

    Used for optimizing Chisel's performance and testing Chisel itself

    Attributes
    protected
    Definition Classes
    Bundle
    Note

    This should not be used in user code!

  25. def as[S <: Data](implicit ev: <:<[ReadyValidIO[T], S]): connectable.Connectable[S]

    Static cast to a super type

    Static cast to a super type

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  26. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  27. macro def asTypeOf[T <: Data](that: T): T

    Does a reinterpret cast of the bits in this node into the format that provides.

    Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.

    x.asTypeOf(that) performs the inverse operation of x := that.toBits.

    Definition Classes
    Data
    Note

    bit widths are NOT checked, may pad or drop bits from input

    ,

    that should have known widths

  28. final macro def asUInt: UInt

    Reinterpret cast to UInt.

    Reinterpret cast to UInt.

    Definition Classes
    Data
    Note

    value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7

    ,

    Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.

  29. def autoSeed(name: String): ReadyValidIO.this.type

    Takes the last seed suggested.

    Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).

    If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.

    Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.

    returns

    this object

    Definition Classes
    Data → HasId
  30. val base: ReadyValidIO[T]
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  31. def binding: Option[Binding]
    Attributes
    protected[chisel3]
    Definition Classes
    Data
  32. def binding_=(target: Binding): Unit
    Attributes
    protected
    Definition Classes
    Data
  33. val bits: T

    The data to be transferred when ready and valid are asserted at the same cycle

  34. def circuitName: String
    Definition Classes
    HasId
  35. def className: String

    Name for Pretty Printing

    Name for Pretty Printing

    Definition Classes
    BundleRecord
  36. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native()
  37. def cloneType: ReadyValidIO.this.type

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    cloneType must be defined for any Chisel object extending Data. It is responsible for constructing a basic copy of the object being cloned.

    returns

    a copy of the object.

    Definition Classes
    RecordData
  38. def containsAFlipped: Boolean
    Definition Classes
    RecordData
  39. def deq(): T

    Assert ready on this port and return the associated data bits.

    Assert ready on this port and return the associated data bits. This is typically used when valid has been asserted by the producer side.

    returns

    The data bits.

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toAddMethodsToReadyValid[T] performed by method AddMethodsToReadyValid in chisel3.util.ReadyValidIO.This conversion will take place only if T is a subclass of Data (T <: Data).
    Definition Classes
    AddMethodsToReadyValid
  40. def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo): T

    Definition Classes
    Data
  41. def do_asUInt(implicit sourceInfo: SourceInfo): UInt

    Definition Classes
    Data
  42. final lazy val elements: SeqMap[String, Data]

    The collection of Data

    The collection of Data

    Elements defined earlier in the Bundle are higher order upon serialization. For example:

    Definition Classes
    BundleRecord
    Example:
    1. class MyBundle extends Bundle {
        val foo = UInt(16.W)
        val bar = UInt(16.W)
      }
      // Note that foo is higher order because its defined earlier in the Bundle
      val bundle = Wire(new MyBundle)
      bundle.foo := 0x1234.U
      bundle.bar := 0x5678.U
      val uint = bundle.asUInt
      assert(uint === "h12345678".U) // This will pass
  43. def enq(dat: T): T

    Push dat onto the output bits of this interface to let the consumer know it has happened.

    Push dat onto the output bits of this interface to let the consumer know it has happened.

    dat

    the values to assign to bits.

    returns

    dat.

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toAddMethodsToReadyValid[T] performed by method AddMethodsToReadyValid in chisel3.util.ReadyValidIO.This conversion will take place only if T is a subclass of Data (T <: Data).
    Definition Classes
    AddMethodsToReadyValid
  44. def ensuring(cond: (ReadyValidIO[T]) => Boolean, msg: => Any): ReadyValidIO[T]
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toEnsuring[ReadyValidIO[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  45. def ensuring(cond: (ReadyValidIO[T]) => Boolean): ReadyValidIO[T]
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toEnsuring[ReadyValidIO[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  46. def ensuring(cond: Boolean, msg: => Any): ReadyValidIO[T]
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toEnsuring[ReadyValidIO[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  47. def ensuring(cond: Boolean): ReadyValidIO[T]
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toEnsuring[ReadyValidIO[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  48. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  49. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  50. def exclude(members: (ReadyValidIO[T]) => Data*): connectable.Connectable[ReadyValidIO[T]]

    Select members of base to exclude

    Select members of base to exclude

    members

    functions given the base return a member to exclude

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  51. def exclude: connectable.Connectable[ReadyValidIO[T]]

    Adds base to excludes

    Adds base to excludes

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  52. def excludeAs[S <: Data](members: (ReadyValidIO[T]) => Data*)(implicit ev: <:<[ReadyValidIO[T], S]): connectable.Connectable[S]

    Select members of base to exclude and static cast to a new type

    Select members of base to exclude and static cast to a new type

    members

    functions given the base return a member to exclude

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  53. def excludeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[ReadyValidIO[T], S]): connectable.Connectable[S]

    Programmatically select members of base to exclude and static cast to a new type

    Programmatically select members of base to exclude and static cast to a new type

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  54. def excludeProbes: connectable.Connectable[ReadyValidIO[T]]

    Exclude probes

    Exclude probes

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  55. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable])
  56. def fire: Bool

    Indicates if IO is both ready and valid

    Indicates if IO is both ready and valid

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toAddMethodsToReadyValid[T] performed by method AddMethodsToReadyValid in chisel3.util.ReadyValidIO.This conversion will take place only if T is a subclass of Data (T <: Data).
    Definition Classes
    AddMethodsToReadyValid
  57. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  58. def getElements: Seq[Data]

    Returns a Seq of the immediate contents of this Aggregate, in order.

    Returns a Seq of the immediate contents of this Aggregate, in order.

    Definition Classes
    RecordAggregate
  59. final def getWidth: Int

    Returns the width, in bits, if currently known.

    Returns the width, in bits, if currently known.

    Definition Classes
    Data
  60. def hasSeed: Boolean

    returns

    Whether either autoName or suggestName has been called

    Definition Classes
    HasId
  61. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  62. def ignoreSeq: Boolean

    Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.

    Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.

    Definition Classes
    Bundle
  63. def instanceName: String
    Definition Classes
    HasId → InstanceId
  64. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  65. def isLit: Boolean
    Definition Classes
    Data
  66. final def isWidthKnown: Boolean

    Returns whether the width is currently known.

    Returns whether the width is currently known.

    Definition Classes
    Data
  67. def litOption: Option[BigInt]

    Return an Aggregate's literal value if it is a literal, None otherwise.

    Return an Aggregate's literal value if it is a literal, None otherwise. If any element of the aggregate is not a literal with a defined width, the result isn't a literal.

    returns

    an Aggregate's literal value if it is a literal.

    Definition Classes
    AggregateData
  68. def litValue: BigInt

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Definition Classes
    AggregateData
  69. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  70. def nodeq(): Unit

    Indicate no dequeue occurs.

    Indicate no dequeue occurs. Ready is set to false.

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toAddMethodsToReadyValid[T] performed by method AddMethodsToReadyValid in chisel3.util.ReadyValidIO.This conversion will take place only if T is a subclass of Data (T <: Data).
    Definition Classes
    AddMethodsToReadyValid
  71. def noenq(): Unit

    Indicate no enqueue occurs.

    Indicate no enqueue occurs. Valid is set to false, and bits are connected to an uninitialized wire.

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toAddMethodsToReadyValid[T] performed by method AddMethodsToReadyValid in chisel3.util.ReadyValidIO.This conversion will take place only if T is a subclass of Data (T <: Data).
    Definition Classes
    AddMethodsToReadyValid
  72. def notWaivedOrSqueezedOrExcluded: Boolean

    True if no members are waived or squeezed or excluded

    True if no members are waived or squeezed or excluded

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  73. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  74. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  75. def parentModName: String
    Definition Classes
    HasId → InstanceId
  76. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  77. def pathName: String
    Definition Classes
    HasId → InstanceId
  78. val ready: Bool

    Indicates that the consumer is ready to accept the data this cycle

  79. def squeeze(members: (ReadyValidIO[T]) => Data*): connectable.Connectable[ReadyValidIO[T]]

    Select members of base to squeeze

    Select members of base to squeeze

    members

    functions given the base return a member to squeeze

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  80. def squeeze: connectable.Connectable[ReadyValidIO[T]]

    Adds base to squeezes

    Adds base to squeezes

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  81. def squeezeAll: connectable.Connectable[ReadyValidIO[T]]

    Squeeze all members of base

    Squeeze all members of base

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  82. def squeezeAllAs[S <: Data](implicit ev: <:<[ReadyValidIO[T], S]): connectable.Connectable[S]

    Squeeze all members of base and upcast to super type

    Squeeze all members of base and upcast to super type

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  83. def squeezeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]]): connectable.Connectable[ReadyValidIO[T]]

    Programmatically select members of base to squeeze

    Programmatically select members of base to squeeze

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  84. def suggestName(seed: => String): ReadyValidIO.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

    seed

    The seed for the name of this component

    returns

    this object

    Definition Classes
    HasId
  85. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  86. final def toAbsoluteTarget: ReferenceTarget

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Definition Classes
    NamedComponent → InstanceId
  87. final def toNamed: ComponentName

    Returns a FIRRTL ComponentName that references this object

    Returns a FIRRTL ComponentName that references this object

    Definition Classes
    NamedComponent → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  88. def toPrintable: Printable

    Default "pretty-print" implementation Analogous to printing a Map Results in "Bundle(elt0.name -> elt0.value, ...)"

    Default "pretty-print" implementation Analogous to printing a Map Results in "Bundle(elt0.name -> elt0.value, ...)"

    Definition Classes
    BundleRecordData
    Note

    The order is reversed from the order of elements in order to print the fields in the order they were defined

  89. final def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    NamedComponent
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The NamedComponent must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  90. def toString(): String

    The collection of chisel3.Data

    The collection of chisel3.Data

    This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to Vec). For example:

    // Assume we have some type MyRecord that creates a Record from the ListMap
    val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W)))
    // "buzz" is higher order because it was added later than "fizz"
    record("fizz") := "hdead".U
    record("buzz") := "hbeef".U
    val uint = record.asUInt
    assert(uint === "hbeefdead".U) // This will pass
    Definition Classes
    Record → AnyRef → Any
  91. final def toTarget: ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object

    Returns a FIRRTL ReferenceTarget that references this object

    Definition Classes
    NamedComponent → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  92. def typeName: String

    A stable typeName for this ReadyValidIO and any of its implementations using the supplied Data generator's typeName

    A stable typeName for this ReadyValidIO and any of its implementations using the supplied Data generator's typeName

    Definition Classes
    ReadyValidIOData
  93. def unsafe: connectable.Connectable[Data]

    Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members

    Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  94. val valid: Bool

    Indicates that the producer has put valid data in 'bits'

  95. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  96. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  97. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()
  98. def waive(members: (ReadyValidIO[T]) => Data*): connectable.Connectable[ReadyValidIO[T]]

    Select members of base to waive

    Select members of base to waive

    members

    functions given the base return a member to waive

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  99. def waiveAll: connectable.Connectable[ReadyValidIO[T]]

    Waive all members of base

    Waive all members of base

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  100. def waiveAllAs[S <: Data](implicit ev: <:<[ReadyValidIO[T], S]): connectable.Connectable[S]

    Waive all members of base and static cast to a new type

    Waive all members of base and static cast to a new type

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  101. def waiveAs[S <: Data](members: (ReadyValidIO[T]) => Data*)(implicit ev: <:<[ReadyValidIO[T], S]): connectable.Connectable[S]

    Select members of base to waive and static cast to a new type

    Select members of base to waive and static cast to a new type

    members

    functions given the base return a member to waive

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  102. def waiveEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[ReadyValidIO[T], S]): connectable.Connectable[S]

    Programmatically select members of base to waive and static cast to a new type

    Programmatically select members of base to waive and static cast to a new type

    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toConnectable[ReadyValidIO[T]] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  103. final def widthOption: Option[Int]

    Returns Some(width) if the width is known, else None.

    Returns Some(width) if the width is known, else None.

    Definition Classes
    Data

Deprecated Value Members

  1. def formatted(fmtstr: String): String
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toStringFormat[ReadyValidIO[T]] performed by method StringFormat in scala.Predef.
    Definition Classes
    StringFormat
    Annotations
    @deprecated @inline()
    Deprecated

    (Since version 2.12.16) Use formatString.format(value) instead of value.formatted(formatString), or use the f"" string interpolator. In Java 15 and later, formatted resolves to the new method in String which has reversed parameters.

  2. def [B](y: B): (ReadyValidIO[T], B)
    Implicit
    This member is added by an implicit conversion from ReadyValidIO[T] toArrowAssoc[ReadyValidIO[T]] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @deprecated
    Deprecated

    (Since version 2.13.0) Use -> instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.

Inherited from Bundle

Inherited from Record

Inherited from Aggregate

Inherited from Data

Inherited from SourceInfoDoc

Inherited from NamedComponent

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Inherited by implicit conversion AddMethodsToReadyValid fromReadyValidIO[T] to AddMethodsToReadyValid[T]

Inherited by implicit conversion DataEquality fromReadyValidIO[T] to DataEquality[ReadyValidIO[T]]

Inherited by implicit conversion toConnectableDefault fromReadyValidIO[T] to Connectable[ReadyValidIO[T]]

Inherited by implicit conversion ConnectableDefault fromReadyValidIO[T] to ConnectableDefault[ReadyValidIO[T]]

Inherited by implicit conversion any2stringadd fromReadyValidIO[T] to any2stringadd[ReadyValidIO[T]]

Inherited by implicit conversion StringFormat fromReadyValidIO[T] to StringFormat[ReadyValidIO[T]]

Inherited by implicit conversion Ensuring fromReadyValidIO[T] to Ensuring[ReadyValidIO[T]]

Inherited by implicit conversion ArrowAssoc fromReadyValidIO[T] to ArrowAssoc[ReadyValidIO[T]]

Signals

The actual hardware fields of the Bundle

connection

Ungrouped

SourceInfoTransformMacro

These internal methods are not part of the public-facing API!

The equivalent public-facing methods do not have the do_ prefix or have the same name. Use and look at the documentation for those. If you want left shift, use <<, not do_<<. If you want conversion to a Seq of Bools look at the asBools above, not the one below. Users can safely ignore every method in this group!

🐉🐉🐉 Here be dragons... 🐉🐉🐉

These do_X methods are used to enable both implicit passing of SourceInfo while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your designs, are converted to their "hidden", do_*, via macro transformations. Without using macros here, only one of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a chained apply as an explicit 'implicit' argument and will throw type errors.

The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method into a call to an internal, hidden do_* that takes an explicit SourceInfo by inserting an implicitly[SourceInfo] as the explicit argument.