Packages

abstract class ReadyValidIO[+T <: Data] extends Bundle

An I/O Bundle containing 'valid' and 'ready' signals that handshake the transfer of data stored in the 'bits' subfield. The base protocol implied by the directionality is that the producer uses the interface as-is (outputs bits) while the consumer uses the flipped interface (inputs bits). The actual semantics of ready/valid are enforced via the use of concrete subclasses.

Source
Decoupled.scala
Linear Supertypes
Bundle, Record, Aggregate, Data, SourceInfoDoc, NamedComponent, HasId, internal.InstanceId, AnyRef, Any
Known Subclasses
Ordering
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Inherited
  1. ReadyValidIO
  2. Bundle
  3. Record
  4. Aggregate
  5. Data
  6. SourceInfoDoc
  7. NamedComponent
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new ReadyValidIO(gen: T)

    gen

    the type of data to be wrapped in Ready/Valid

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def :=(that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit

    Connect this data to that data mono-directionally and element-wise.

    Connect this data to that data mono-directionally and element-wise.

    This uses the MonoConnect algorithm.

    that

    the data to connect to

    Definition Classes
    Data
  4. final def <>(that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit

    Connect this data to that data bi-directionally and element-wise.

    Connect this data to that data bi-directionally and element-wise.

    This uses the BiConnect algorithm.

    that

    the data to connect to

    Definition Classes
    Data
  5. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  6. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  7. macro def asTypeOf[T <: Data](that: T): T

    Does a reinterpret cast of the bits in this node into the format that provides.

    Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.

    x.asTypeOf(that) performs the inverse operation of x := that.toBits.

    Definition Classes
    Data
    Note

    bit widths are NOT checked, may pad or drop bits from input

    ,

    that should have known widths

  8. final macro def asUInt(): UInt

    Reinterpret cast to UInt.

    Reinterpret cast to UInt.

    Definition Classes
    Data
    Note

    value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7

    ,

    Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.

  9. def binding: Option[Binding]
    Attributes
    protected[chisel3]
    Definition Classes
    Data
  10. def bindingToString: String
    Attributes
    protected
    Definition Classes
    Data
  11. def binding_=(target: Binding): Unit
    Attributes
    protected
    Definition Classes
    Data
  12. val bits: T
  13. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  14. def className: String

    Name for Pretty Printing

    Name for Pretty Printing

    Definition Classes
    BundleRecord
  15. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  16. def cloneType: ReadyValidIO.this.type

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    cloneType must be defined for any Chisel object extending Data. It is responsible for constructing a basic copy of the object being cloned.

    returns

    a copy of the object.

    Definition Classes
    BundleData
  17. def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T

    Definition Classes
    Data
  18. def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt

    Definition Classes
    AggregateData
  19. final lazy val elements: ListMap[String, Data]

    The collection of Data

    The collection of Data

    Elements defined earlier in the Bundle are higher order upon serialization. For example:

    Definition Classes
    BundleRecord
    Example:
    1. class MyBundle extends Bundle {
        val foo = UInt(16.W)
        val bar = UInt(16.W)
      }
      // Note that foo is higher order because its defined earlier in the Bundle
      val bundle = Wire(new MyBundle)
      bundle.foo := 0x1234.U
      bundle.bar := 0x5678.U
      val uint = bundle.asUInt
      assert(uint === "h12345678".U) // This will pass
  20. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  21. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  22. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  23. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  24. def getElements: Seq[Data]

    Returns a Seq of the immediate contents of this Aggregate, in order.

    Returns a Seq of the immediate contents of this Aggregate, in order.

    Definition Classes
    RecordAggregate
  25. final def getWidth: Int

    Returns the width, in bits, if currently known.

    Returns the width, in bits, if currently known.

    Definition Classes
    Data
  26. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  27. def ignoreSeq: Boolean

    Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.

    Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.

    Definition Classes
    Bundle
  28. def instanceName: String
    Definition Classes
    HasId → InstanceId
  29. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  30. def isLit(): Boolean
    Definition Classes
    Data
  31. final def isWidthKnown: Boolean

    Returns whether the width is currently known.

    Returns whether the width is currently known.

    Definition Classes
    Data
  32. def litOption(): Option[BigInt]

    If this is a literal that is representable as bits, returns the value as a BigInt.

    If this is a literal that is representable as bits, returns the value as a BigInt. If not a literal, or not representable as bits (for example, is or contains Analog), returns None.

    Definition Classes
    AggregateData
  33. def litValue(): BigInt

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Definition Classes
    Data
  34. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  35. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  36. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  37. def parentModName: String
    Definition Classes
    HasId → InstanceId
  38. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  39. def pathName: String
    Definition Classes
    HasId → InstanceId
  40. val ready: Bool
  41. def suggestName(name: ⇒ String): ReadyValidIO.this.type
    Definition Classes
    HasId
  42. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  43. final def toAbsoluteTarget: ReferenceTarget

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Definition Classes
    NamedComponent → InstanceId
  44. def toPrintable: Printable

    Default "pretty-print" implementation Analogous to printing a Map Results in "Bundle(elt0.name -> elt0.value, ...)"

    Default "pretty-print" implementation Analogous to printing a Map Results in "Bundle(elt0.name -> elt0.value, ...)"

    Definition Classes
    BundleRecordData
    Note

    The order is reversed from the order of elements in order to print the fields in the order they were defined

  45. def toString(): String

    The collection of Data

    The collection of Data

    This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to Vec). For example:

    // Assume we have some type MyRecord that creates a Record from the ListMap
    val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W)))
    // "buzz" is higher order because it was added later than "fizz"
    record("fizz") := "hdead".U
    record("buzz") := "hbeef".U
    val uint = record.asUInt
    assert(uint === "hbeefdead".U) // This will pass
    Definition Classes
    Record → AnyRef → Any
  46. final def toTarget: ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object

    Returns a FIRRTL ReferenceTarget that references this object

    Definition Classes
    NamedComponent → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  47. val valid: Bool
  48. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  49. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  50. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  51. final def widthOption: Option[Int]

    Returns Some(width) if the width is known, else None.

    Returns Some(width) if the width is known, else None.

    Definition Classes
    Data

Deprecated Value Members

  1. def litArg(): Option[LitArg]
    Definition Classes
    Data
    Annotations
    @chiselRuntimeDeprecated() @deprecated
    Deprecated

    (Since version 3.2) litArg is deprecated, use litOption or litTo*Option

  2. final def toNamed: ComponentName

    Returns a FIRRTL ComponentName that references this object

    Returns a FIRRTL ComponentName that references this object

    Definition Classes
    NamedComponent → InstanceId
    Annotations
    @deprecated
    Deprecated

    (Since version 3.2) toNamed API is deprecated -- use toTarget instead

    Note

    Should not be called until circuit elaboration is complete

Inherited from Bundle

Inherited from Record

Inherited from Aggregate

Inherited from Data

Inherited from SourceInfoDoc

Inherited from NamedComponent

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

Connect

Utilities for connecting hardware components

Ungrouped

SourceInfoTransformMacro

These internal methods are not part of the public-facing API!

The equivalent public-facing methods do not have the do_ prefix or have the same name. Use and look at the documentation for those. If you want left shift, use <<, not do_<<. If you want conversion to a Seq of Bools look at the asBools above, not the one below. Users can safely ignore every method in this group!

🐉🐉🐉 Here be dragons... 🐉🐉🐉

These do_X methods are used to enable both implicit passing of SourceInfo and chisel3.CompileOptions while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your designs, are converted to their "hidden", do_*, via macro transformations. Without using macros here, only one of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a chained apply as an explicit 'implicit' argument and will throw type errors.

The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method into a call to an internal, hidden do_* that takes an explicit SourceInfo by inserting an implicitly[SourceInfo] as the explicit argument.