Packages

  • package root

    This is the documentation for Chisel.

    This is the documentation for Chisel.

    Package structure

    The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

    The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

    Utility objects and methods are found in the util package.

    The testers package defines the basic interface for chisel testers.

    Definition Classes
    root
  • package chisel3

    This package contains the main chisel3 API.

    This package contains the main chisel3 API.

    Definition Classes
    root
  • package util

    The util package provides extensions to core chisel for common hardware components and utility functions

    The util package provides extensions to core chisel for common hardware components and utility functions

    Definition Classes
    chisel3
  • package circt
    Definition Classes
    util
  • package dpi
  • ClockGate
  • IsX
  • Mux2Cell
  • Mux4Cell
  • PlusArgsRetBundle
  • PlusArgsTest
  • PlusArgsValue
  • SizeOf
  • package experimental
    Definition Classes
    util
  • package random
    Definition Classes
    util

package circt

Ordering
  1. Alphabetic
Visibility
  1. Public
  2. Protected

Package Members

  1. package dpi

Type Members

  1. class PlusArgsRetBundle[T <: Data] extends Bundle

Value Members

  1. object ClockGate
  2. object IsX
  3. object Mux2Cell

    Utility for constructing 2-to-1 MUX cell intrinsic.

    Utility for constructing 2-to-1 MUX cell intrinsic. This intrinsic is lowered into verilog with vendor specic pragmas that guarantee utilization of 2-to-1 MUX cell in the synthesis process. Semantically Mux2Cell(cond, con, alt) is equivalent to Mux(cond, con, alt) for all cond, con and alt.

  4. object Mux4Cell

    Utility for constructing 4-to-1 MUX cell intrinsic.

    Utility for constructing 4-to-1 MUX cell intrinsic. This intrinsic is lowered into verilog with vendor specic pragmas that guarantee utilization of 4-to-1 MUX cell in the synthesis process.

  5. object PlusArgsTest
  6. object PlusArgsValue

    Create an intrinsic which generates a verilog $value$plusargs.

    Create an intrinsic which generates a verilog $value$plusargs. This returns a value as indicated by the format string and a flag for whether the value was found.

  7. object SizeOf

Ungrouped