object Mux4Cell
Utility for constructing 4-to-1 MUX cell intrinsic. This intrinsic is lowered into verilog with vendor specic pragmas that guarantee utilization of 4-to-1 MUX cell in the synthesis process.
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- Synthesis.scala
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Creates an intrinsic which will be lowered to a 4-to-1 MUX cell in synthesis tools.
Creates an intrinsic which will be lowered to a 4-to-1 MUX cell in synthesis tools.
- sel
2-bit unsigned integer determining the input to choose.
- v3
the value chosen when
selectoris3- v2
the value chosen when
selectoris2- v1
the value chosen when
selectoris1- v0
the value chosen when
selectoris0
v := Mux4Cell(sel, v3, v2, v1, v0)
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.