Packages

  • package root

    This is the documentation for Chisel.

    This is the documentation for Chisel.

    Package structure

    The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

    The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

    Utility objects and methods are found in the util package.

    The testers package defines the basic interface for chisel testers.

    Definition Classes
    root
  • package chisel3

    This package contains the main chisel3 API.

    This package contains the main chisel3 API.

    Definition Classes
    root
  • package util

    The util package provides extensions to core chisel for common hardware components and utility functions

    The util package provides extensions to core chisel for common hardware components and utility functions

    Definition Classes
    chisel3
  • package circt
    Definition Classes
    util
  • package dpi
    Definition Classes
    circt
  • ClockGate
  • IsX
  • Mux2Cell
  • Mux4Cell
  • PlusArgsRetBundle
  • PlusArgsTest
  • PlusArgsValue
  • SizeOf

object Mux2Cell

Utility for constructing 2-to-1 MUX cell intrinsic. This intrinsic is lowered into verilog with vendor specic pragmas that guarantee utilization of 2-to-1 MUX cell in the synthesis process. Semantically Mux2Cell(cond, con, alt) is equivalent to Mux(cond, con, alt) for all cond, con and alt.

Source
Synthesis.scala
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  1. final def !=(arg0: Any): Boolean
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  3. final def ==(arg0: Any): Boolean
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  4. def apply[T <: Data](cond: UInt, con: T, alt: T): T

    Creates an intrinsic which will be lowered to a 2-to-1 MUX cell in synthesis tools.

    Creates an intrinsic which will be lowered to a 2-to-1 MUX cell in synthesis tools.

    cond

    condition determining the input to choose

    con

    the value chosen when cond is true

    alt

    the value chosen when cond is false

    Example:

    1. val muxOut = Mux2Cell(data_in === 3.U, 3.U(4.W), 0.U(4.W))
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