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o

chisel3.util

ShiftRegister

object ShiftRegister extends ShiftRegisterIntf

Source
Reg.scala
Linear Supertypes
ShiftRegisterIntf, AnyRef, Any
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  1. ShiftRegister
  2. ShiftRegisterIntf
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Visibility
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Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def _applyImpl[T <: Data](in: T, n: Int, resetData: T, en: Bool)(implicit sourceInfo: SourceInfo): T
    Attributes
    protected
  5. def _applyImpl[T <: Data](in: T, n: Int, en: Bool = true.B)(implicit sourceInfo: SourceInfo): T
    Attributes
    protected
  6. def _applyImplMem[T <: Data](in: T, n: Int, en: Bool = true.B, useDualPortSram: Boolean = false, name: Option[String] = None)(implicit sourceInfo: SourceInfo): T
    Attributes
    protected
  7. macro def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T

    Returns the n-cycle delayed version of the input signal with reset initialization.

    Returns the n-cycle delayed version of the input signal with reset initialization.

    in

    input to delay

    n

    number of cycles to delay

    resetData

    reset value for each register in the shift

    en

    enable the shift

    Definition Classes
    ShiftRegisterIntf
    Example:
    1. val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena)
  8. macro def apply[T <: Data](in: T, n: Int): T

    Returns the n-cycle delayed version of the input signal.

    Returns the n-cycle delayed version of the input signal.

    Enable is assumed to be true.

    in

    input to delay

    n

    number of cycles to delay

    Definition Classes
    ShiftRegisterIntf
    Example:
    1. val regDelayTwo = ShiftRegister(nextVal, 2)
  9. macro def apply[T <: Data](in: T, n: Int, en: Bool): T

    Returns the n-cycle delayed version of the input signal.

    Returns the n-cycle delayed version of the input signal.

    in

    input to delay

    n

    number of cycles to delay

    en

    enable the shift

    Definition Classes
    ShiftRegisterIntf
    Example:
    1. val regDelayTwo = ShiftRegister(nextVal, 2, ena)
  10. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  11. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native()
  12. def do_apply[T <: Data](in: T, n: Int, resetData: T, en: Bool)(implicit sourceInfo: SourceInfo): T

    Definition Classes
    ShiftRegisterIntf
  13. def do_apply[T <: Data](in: T, n: Int)(implicit sourceInfo: SourceInfo): T

    Definition Classes
    ShiftRegisterIntf
  14. def do_apply[T <: Data](in: T, n: Int, en: Bool = true.B)(implicit sourceInfo: SourceInfo): T

    Definition Classes
    ShiftRegisterIntf
  15. def do_mem[T <: Data](in: T, n: Int, en: Bool, useDualPortSram: Boolean, name: Option[String])(implicit sourceInfo: SourceInfo): T

    Definition Classes
    ShiftRegisterIntf
  16. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  17. def equals(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef → Any
  18. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable])
  19. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  20. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  21. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  22. macro def mem[T <: Data](in: T, n: Int, en: Bool, useDualPortSram: Boolean, name: Option[String]): T

    Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).

    Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).

    in

    input to delay

    n

    number of cycles to delay

    en

    enable the shift

    useDualPortSram

    dual port or single port SRAM based implementation

    name

    name of SyncReadMem object

    Definition Classes
    ShiftRegisterIntf
  23. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  24. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  25. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  26. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  27. def toString(): String
    Definition Classes
    AnyRef → Any
  28. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  29. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  30. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()

Inherited from ShiftRegisterIntf

Inherited from AnyRef

Inherited from Any

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