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1.  final def !=(arg0: Any): Boolean

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2.  final def ##: Int

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3.  final def ==(arg0: Any): Boolean

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4.  def apply(table: Seq[(BitPat, BitPat)], invert: BitPat = BitPat("b0")): (UInt, UInt)

   Construct a https://en.wikipedia.org/wiki/Programmable_logic_array from specified table.

   Construct a https://en.wikipedia.org/wiki/Programmable_logic_array from specified table.

   Each position in the input matrix corresponds to an input variable where 0 implies the corresponding input literal appears complemented in the product term. 1 implies the input literal appears uncomplemented in the product term ? implies the input literal does not appear in the product term.

   For each output a 1 means this product term makes the function value to 1 and a 0 or ? means this product term make the function value to 0

   table

   A Seq of inputs -> outputs mapping

   invert

   A BitPat specify which bit of the output should be inverted. 1 means the correspond position of the output should be inverted in the PLA, a 0 or a ? means direct output from the OR matrix.

   returns

   the (input, output) Wire of UInt of the constructed pla.

   // A 1-of-8 decoder (like the 74xx138) can be constructed as follow
   val (inputs, outputs) = pla(Seq(
     (BitPat("b000"), BitPat("b00000001")),
     (BitPat("b001"), BitPat("b00000010")),
     (BitPat("b010"), BitPat("b00000100")),
     (BitPat("b011"), BitPat("b00001000")),
     (BitPat("b100"), BitPat("b00010000")),
     (BitPat("b101"), BitPat("b00100000")),
     (BitPat("b110"), BitPat("b01000000")),
     (BitPat("b111"), BitPat("b10000000")),
   ))

   Note

   There is one special case which we call it ? -> 1. In this scenario, for some of the output functions (bits), all input terms that make this function value to 1 is purely composed by ?. In a real pla, this will result in no connection to the gates in the AND Plane (verilog z on gate inputs), which in turn makes the outputs of the AND Plane undetermined (verilog x on outputs). This is not desired behavior in most cases, for example the minimization result of following truth table: 0 -> 1 1 -> 1 which is: ? -> 1 actually means something other than a verilog x. To ease the generation of minimized truth tables, this pla generation api will hard wire outputs to a 1 on this special case. This behavior is formally described as: if product terms that make one function value to 1 is solely consisted of don't-cares (?s), then this function is implemented as a constant 1.

5.  final def asInstanceOf[T0]: T0

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6.  def clone(): AnyRef

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7.  final def eq(arg0: AnyRef): Boolean

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8.  def equals(arg0: AnyRef): Boolean

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9.  def finalize(): Unit

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10.  final def getClass(): Class[_ <: AnyRef]

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11.  def hashCode(): Int

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12.  final def isInstanceOf[T0]: Boolean

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13.  final def ne(arg0: AnyRef): Boolean

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14.  final def notify(): Unit

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15.  final def notifyAll(): Unit

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16.  final def synchronized[T0](arg0: => T0): T0

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17.  def toString(): String

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18.  final def wait(): Unit

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19.  final def wait(arg0: Long, arg1: Int): Unit

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20.  final def wait(arg0: Long): Unit

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