object ChiselStage

Utilities for compiling Chisel

Source
ChiselStage.scala
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  6. def convert(gen: => RawModule, args: Array[String] = Array.empty): Circuit

    Return a CHIRRTL circuit for a Chisel module

    Return a CHIRRTL circuit for a Chisel module

    gen

    a call-by-name Chisel module

  7. def emitCHIRRTL(gen: => RawModule, args: Array[String] = Array.empty): String

    Elaborate a Chisel circuit into a CHIRRTL string

  8. def emitCHIRRTLFile(gen: => RawModule, args: Array[String] = Array.empty): AnnotationSeq

    Elaborates a Chisel circuit and emits it to a file

    Elaborates a Chisel circuit and emits it to a file

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel

  9. def emitFIRRTLDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

    Compile a Chisel circuit to FIRRTL dialect

  10. def emitHWDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

    Compile a Chisel circuit to HWS dialect

  11. def emitSystemVerilog(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

    Compile a Chisel circuit to SystemVerilog

    Compile a Chisel circuit to SystemVerilog

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel

    firtoolOpts

    additional circt.stage.FirtoolOption to pass to firtool

    returns

    a string containing the Verilog output

  12. def emitSystemVerilogFile(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): AnnotationSeq

    Compile a Chisel circuit to SystemVerilog with file output

    Compile a Chisel circuit to SystemVerilog with file output

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel

    firtoolOpts

    additional command line options to pass to firtool

    returns

    a string containing the Verilog output

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