package phases
Type Members
- class AddImplicitOutputFile extends Phase
Phase that adds an OutputFileAnnotation if one does not already exist.
Phase that adds an OutputFileAnnotation if one does not already exist.
To determine the OutputFileAnnotation, the following precedence is used. Whichever happens first succeeds:
- Do nothing if an OutputFileAnnotation "--split-verilog" was specified
- Use the main in the first discovered FirrtlCircuitAnnotation (see note below)
- Use "a"
- class CIRCT extends Phase
A phase that calls and runs CIRCT, specifically
firtool
, while preserving an AnnotationSeq API. - class Checks extends Phase
Check properties of an firrtl.AnnotationSeq! to look for errors before running CIRCT.
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.