Packages

•  package root

  This is the documentation for Chisel.

  This is the documentation for Chisel.

  Package structure

  The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

  The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

  Utility objects and methods are found in the util package.

  The testers package defines the basic interface for chisel testers.

  Definition Classes

  root

•  package chiseltest

  ChiselTest Compatibility Layer for Chisel 7

  ChiselTest Compatibility Layer for Chisel 7

  This package provides a drop-in replacement for the ChiselTest library that was removed in Chisel 7. It preserves the familiar ChiselTest API while delegating to Chisel 7's ChiselSim underneath.

  Usage:

  import chiseltest._
  import org.scalatest.flatspec.AnyFlatSpec
  
  class MyTest extends AnyFlatSpec with ChiselScalatestTester {
    it should "work" in {
      test(new MyModule) { dut =>
        dut.io.in.poke(42.U)
        dut.clock.step()
        dut.io.out.expect(42.U)
      }
    }
  }

  Key Components: - testableData, testableUInt, testableBoolExt: Implicit conversions for poke/peek/expect - testableClock: Clock stepping and control - DecoupledIOOps: Utilities for Decoupled interface testing - ChiselScalatestTester: ScalaTest integration trait

  See README.md for detailed documentation.

  Definition Classes

  root

•  trait ChiselScalatestTester extends AnyRef

  ChiselTest-compatible API that delegates to ChiselSim (Chisel 7)

  ChiselTest-compatible API that delegates to ChiselSim (Chisel 7)

  This trait provides the ChiselTest API that users are familiar with from Chisel 6, but internally uses ChiselSim from Chisel 7 to perform the actual testing.

  VCD GENERATION SUPPORT: This compatibility layer supports VCD generation when WriteVcdAnnotation is used. VCD files are generated in: build/chiselsim/<timestamp>/workdir-verilator/trace.vcd

  AUTOMATIC RESET FEATURE: By default, this trait automatically resets the module before running tests, mimicking ChiselTest's behavior from Chisel 6.

  To disable auto-reset or customize the reset duration:

  class MyTest extends AnyFlatSpec with ChiselScalatestTester {
    override def autoResetEnabled: Boolean = false  // Disable auto-reset
    override def resetCycles: Int = 5               // Or change duration
  }

  Example usage with VCD:

  import chiseltest._
  import org.scalatest.flatspec.AnyFlatSpec
  
  class MyModuleSpec extends AnyFlatSpec with ChiselScalatestTester {
    behavior of "MyModule"
  
    it should "generate waveforms" in {
      test(new MyModule).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
        dut.io.in.poke(42.U)
        dut.clock.step()
        dut.io.out.expect(42.U)
      }
      // VCD file: build/chiselsim/<timestamp>/workdir-verilator/trace.vcd
    }
  }

  Definition Classes

  chiseltest

• TestBuilder
• TestRunner

chiseltest.ChiselScalatestTester

TestRunner