chiseltest
package chiseltest
ChiselTest Compatibility Layer for Chisel 7
This package provides a drop-in replacement for the ChiselTest library that was removed in Chisel 7. It preserves the familiar ChiselTest API while delegating to Chisel 7's ChiselSim underneath.
Usage:
import chiseltest._ import org.scalatest.flatspec.AnyFlatSpec class MyTest extends AnyFlatSpec with ChiselScalatestTester { it should "work" in { test(new MyModule) { dut => dut.io.in.poke(42.U) dut.clock.step() dut.io.out.expect(42.U) } } }
Key Components: - testableData, testableUInt, testableBoolExt: Implicit conversions for poke/peek/expect - testableClock: Clock stepping and control - DecoupledIOOps: Utilities for Decoupled interface testing - ChiselScalatestTester: ScalaTest integration trait
See README.md for detailed documentation.
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Type Members
- trait ChiselScalatestTester extends AnyRef
ChiselTest-compatible API that delegates to ChiselSim (Chisel 7)
ChiselTest-compatible API that delegates to ChiselSim (Chisel 7)
This trait provides the ChiselTest API that users are familiar with from Chisel 6, but internally uses ChiselSim from Chisel 7 to perform the actual testing.
VCD GENERATION SUPPORT: This compatibility layer supports VCD generation when WriteVcdAnnotation is used. VCD files are generated in: build/chiselsim/<timestamp>/workdir-verilator/trace.vcd
AUTOMATIC RESET FEATURE: By default, this trait automatically resets the module before running tests, mimicking ChiselTest's behavior from Chisel 6.
To disable auto-reset or customize the reset duration:
class MyTest extends AnyFlatSpec with ChiselScalatestTester { override def autoResetEnabled: Boolean = false // Disable auto-reset override def resetCycles: Int = 5 // Or change duration }
Example usage with VCD:
import chiseltest._ import org.scalatest.flatspec.AnyFlatSpec class MyModuleSpec extends AnyFlatSpec with ChiselScalatestTester { behavior of "MyModule" it should "generate waveforms" in { test(new MyModule).withAnnotations(Seq(WriteVcdAnnotation)) { dut => dut.io.in.poke(42.U) dut.clock.step() dut.io.out.expect(42.U) } // VCD file: build/chiselsim/<timestamp>/workdir-verilator/trace.vcd } }
- final class DecoupledDriver extends AnyRef
Compatibility placeholder for ChiselTest's DecoupledDriver class.
Compatibility placeholder for ChiselTest's DecoupledDriver class.
Decoupled enqueue/dequeue helpers are provided via implicit extensions in
package object chiseltest. Useimport chiseltest._to access: -enqueueNow,enqueueSeq-expectDequeueNow,expectDequeueSeq-initSource,initSink - implicit final class DecoupledIOOps[T <: Data] extends AnyVal
- class ForkHandle extends AnyRef
- implicit final class testableBoolExt extends AnyVal
- implicit final class testableClock extends AnyVal
- implicit final class testableData[T <: Data] extends AnyVal
- implicit final class testableReset extends AnyVal
- implicit final class testableUInt extends AnyVal
Value Members
- def fork(body: => Unit): ForkHandle
- case object VerilatorBackendAnnotation extends Product with Serializable
- case object WriteVcdAnnotation extends Product with Serializable
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.