Type Members

1.  trait Backend extends AnyRef
2.  trait BackendSettingsModifications extends (Settings) => Settings

   Type class to modify backend comopilation settings

3.  case class CommonCompilationSettings(verilogPreprocessorDefines: Seq[VerilogPreprocessorDefine] = Seq(), optimizationStyle: OptimizationStyle = CommonCompilationSettings.OptimizationStyle.Default, availableParallelism: AvailableParallelism = CommonCompilationSettings.AvailableParallelism.Default, defaultTimescale: Option[Timescale] = Some(CommonCompilationSettings.Timescale.default), libraryExtensions: Option[Seq[String]] = None, libraryPaths: Option[Seq[String]] = None, includeDirs: Option[Seq[String]] = None, fileFilter: PartialFunction[File, Boolean] = PartialFunction.empty, directoryFilter: PartialFunction[File, Boolean] = PartialFunction.empty, simulationSettings: CommonSimulationSettings = CommonSimulationSettings.default) extends Product with Serializable

   Settings supported by all svsim backends.

4.  trait CommonSettingsModifications extends (CommonCompilationSettings) => CommonCompilationSettings
5.  final class CommonSimulationSettings extends AnyRef

   Backend-independent simulation runtime settings

   Backend-independent simulation runtime settings

   Note

   Use CommonSimulationSettings$ methods to create objects of this class.

6.  case class ModuleInfo(name: String, ports: Seq[Port]) extends Product with Serializable
7.  final class PlusArg extends AnyRef

   A key/value pair representing a Verilog plusarg

   A key/value pair representing a Verilog plusarg

   When value is a Some, this acts like a $value$plusargs. When value is None, this acts like a $test$plusargs. I.e., when None, the plusarg is simply set. When Some, the plusarg has a value.

8.  final class Simulation extends AnyRef
9.  final class Workspace extends AnyRef