object convention
Utilities for annotating modules with a port convention. The port convention defines how the ports of a module are transformed while lowering to verilog.
- Source
- Convention.scala
class Inner extends Module { val io = IO(new Bundle{}) } class Top extends Module { val inner = Module(new Inner) convention.scalarized(inner) }
Example:
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- def scalarized[T <: BaseModule](data: T): Unit
Annotate a module as having the "scalarized" port convention.
Annotate a module as having the "scalarized" port convention. With this port convention, the aggregate ports of the module will be fully scalarized.
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.