Stimulus that will apply a standard reset procedure to a Chisel circuit.

The reset procedure is as follows:

time 0: bring everything up using simulator settings time 1: bring reset out of x and deassert it. time 2: assert reset time 3: first clock edge time 4 + n: deassert reset (where n == additionalResetCycles)

This intentionally structured to guarantee the following properties:

1. There is guaranteed to be a time when FIRRTL/Verilog-based randomization can happen at _either_ time 0 or time 1.) 2. If time 1 is used for FIRRTL/Verilog-based randomization, then time 0 can be used for simulator-based initialization, e.g., +vcs+initreg+random. Simulator initialization will race with FIRRTL/Verilog-based randomization and it is critical that they do not happen at the same time. 3. Both FIRRTL/Verilog-based randomization and simulator-based randomization should not occur on a clock edge, e.g., an edge when reset is asserted. This can be yet-another race condition that has to be avoided. 4. Reset always sees a posedge. This avoids problems with asynchronous reset logic behavior where they may (correctly in Verilog) _not_ fire if you bring the design with reset asserted. Note: it would be fine to do an x -> 1 transition to show an edge, however, it looks cleaner to bring reset to 0.