Value Members

1.  final def !=(arg0: Any): Boolean

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2.  final def ##: Int

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3.  final def ==(arg0: Any): Boolean

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4.  final def asInstanceOf[T0]: T0

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5.  def clone(): AnyRef

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   protected[lang]

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   @throws(classOf[java.lang.CloneNotSupportedException]) @native()

6.  final def eq(arg0: AnyRef): Boolean

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7.  def equals(arg0: AnyRef): Boolean

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8.  def finalize(): Unit

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   @throws(classOf[java.lang.Throwable])

9.  final def getClass(): Class[_ <: AnyRef]

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   @native()

10.  def hashCode(): Int

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    @native()

11.  final def isInstanceOf[T0]: Boolean

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12.  final def ne(arg0: AnyRef): Boolean

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13.  final def notify(): Unit

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    @native()

14.  final def notifyAll(): Unit

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    @native()

15.  def random: Randomization

    Randomize everything

    Randomize everything

    This will randomize everything that the FIRRTL/Verilog ABI allows. All Verilog that Chisel produces will have a random two-state value. Verilog that Chisel does not have control of (e.g., blackboxes) will be brought up in a different state unless they opt-in to the FIRRTL/Verilog ABI.

    Non-two-state values (i.e., x)

    Note

    The FIRRTL/Verilog ABI for randomization is undocumented in the FIRRTL ABI specification.

16.  final def synchronized[T0](arg0: => T0): T0

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17.  def toString(): String

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18.  def uninitialized: Randomization

    Randomize nothing

    Randomize nothing

    This will cause the simulation to be brought up in whatever state the simulator brings up a simulation in. If the simulator supports x, then uninitialized hardware will be brought up in x. However, if the simulator is two-state (e.g., Verilator), then it will be brought up in a simulator-dependent state.

19.  final def wait(): Unit

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    @throws(classOf[java.lang.InterruptedException])

20.  final def wait(arg0: Long, arg1: Int): Unit

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    @throws(classOf[java.lang.InterruptedException])

21.  final def wait(arg0: Long): Unit

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    @throws(classOf[java.lang.InterruptedException]) @native()