Check if two Chisel types have the same alignments for all matching members

This means that for matching members in Aggregates, they must have matching member alignments relative to the parent type For matching non-aggregates, they must be the same alignment to their parent type.

Check if two Chisel types are the same type. Internally, this is dispatched to each Chisel type's typeEquivalent function for each type to determine if the types are intended to be equal.

For most types, different parameters should ensure that the types are different. For example, UInt(8.W) and UInt(16.W) are different. Likewise, Records check that both Records have the same elements with the same types.

Equivalent to being structural, alignment, and width type equivalent

Collects all members of base who are aligned w.r.t. base Accepts a collector partial function, rather than a collector function

Recursively collect all expanded member components of a data component, including intermediate aggregate nodes

Collects all members of base who are flipped w.r.t. base Accepts a collector partial function, rather than a collector function

Recursively collect just the leaf components of a data component's children (i.e. anything that isn't a Record or a Vec, but an Element). Probes of aggregates are also considered leaves.

Collects all fields selected by collector within a data and all recursive children fields Accepts a collector partial function, rather than a collector function

Collects over members left and right who have structurally corresponding members in either left and right Accepts a collector partial function, rather than a collector function

Collects over members left and right who have structurally corresponding members in either left and right Can return an optional value for left, right, both or neither Accepts a collector partial function, rather than a collector function

Collects over members left and right who have structurally corresponding members in either left and right Can return an optional value for left, right, both or neither Accepts a full function

Collects over members left and right who have structurally corresponding members in both left and right Accepts a collector partial function, rather than a collector function

Returns a recursive representation of a module's ports with underscore-qualified names

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(Vec(2, UInt(8.W)))
  })
  val extra = IO(Input(UInt(8.W)))
  val delay = RegNext(io.in)
  io.out(0) := delay
  io.out(1) := delay + extra
}
val mod = Module(new MyModule)
DataMirror.fullModulePorts(mod)
// returns: Seq(
//   "clock" -> mod.clock,
//   "reset" -> mod.reset,
//   "io" -> mod.io,
//   "io_out" -> mod.io.out,
//   "io_out_0" -> mod.io.out(0),
//   "io_out_1" -> mod.io.out(1),
//   "io_in" -> mod.io.in,
//   "extra" -> mod.extra
// )

Returns the parent module within which a module instance is instantiated

Check if a given Data is a Probe

Check if the given Data is fully aligned w.r.t base. Chisel version of FIRRTL "passive". All Data are considered fully aligned to themselves regardless of their specified direction or relevant coerced directions of their parents. See collectFlippedDeep.

Check if a given Data is an IO port

Check if a given Data is a Property

Check if a given Data is a Reg

Check if a given Data is visible from the current context

Check if a given Data is a Wire

Returns the ports of a module

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(Vec(2, UInt(8.W)))
  })
  val extra = IO(Input(UInt(8.W)))
  val delay = RegNext(io.in)
  io.out(0) := delay
  io.out(1) := delay + extra
}
val mod = Module(new MyModule)
DataMirror.modulePorts(mod)
// returns: Seq(
//   "clock" -> mod.clock,
//   "reset" -> mod.reset,
//   "io" -> mod.io,
//   "extra" -> mod.extra
// )

Get an early guess for the name of this Data

Warning: it is not guaranteed that this name will end up in the output FIRRTL or Verilog.

Name guesses are not stable and may change due to a subsequent Data.suggestName or plugin-related naming. Name guesses are not necessarily legal Verilog identifiers. Name guesses for elements of Bundles or Records will include periods, and guesses for elements of Vecs will include square brackets.