object RequireProperty extends AssertPropertyLike
Require that a property holds as a pre-condition of a contract. Behaves like
an AssertProperty if used outside of a contract. When used inside of a
contract, the behavior differs depending on how the contract is used in a
formal proof:
- During a proof that the contract is upheld by the surrounding circuit, the
property given to RequireProperty is assumed to hold.
- During a larger proof where the contract is already assumed to be proven,
the property given to RequireProperty is asserted to hold.
Use like RequireProperty(p). See AssertPropertyLike.apply for optional
clock, disable_iff, and label parameters.
- Source
- LTL.scala
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- def apply(cond: Bool, clock: Clock, disable: Disable, label: String)(implicit sourceInfo: SourceInfo): Unit
Assert, assume, or cover that a boolean predicate holds.
Assert, assume, or cover that a boolean predicate holds.
- Definition Classes
- AssertPropertyLike
- def apply(cond: Bool, label: String)(implicit sourceInfo: SourceInfo): Unit
Assert, assume, or cover that a boolean predicate holds.
Assert, assume, or cover that a boolean predicate holds.
- Definition Classes
- AssertPropertyLike
- def apply(cond: Bool)(implicit sourceInfo: SourceInfo): Unit
Assert, assume, or cover that a boolean predicate holds.
Assert, assume, or cover that a boolean predicate holds.
- Definition Classes
- AssertPropertyLike
- def apply(prop: => Property, clock: Option[Clock] = Module.clockOption, disable: Option[Disable] = Module.disableOption, label: Option[String] = None)(implicit sourceInfo: SourceInfo): Unit
Assert, assume, or cover that a property holds.
Assert, assume, or cover that a property holds.
- clock
[optional]: specifies a clock with respect to which all cycle delays in the property are expressed. This is a shorthand for
prop.clock(clock).- disable
[optional]: specifies a condition under which the evaluation of the property is disabled. This is a shorthand for
prop.disable(disable).- label
[optional]: is used to assign a name to the assert, assume, or cover construct in the output language. In SystemVerilog, this is emitted as
label: assert(...).
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- AssertPropertyLike
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- def createIntrinsic(label: Option[String])(implicit sourceInfo: SourceInfo): (Bool, Option[Bool]) => Unit
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- RequireProperty → AssertPropertyLike
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.