object ClockDomain extends Domain
A Clock Domain
This represents a collection of signals that toggle together. This does not necessarily mean that signals associated with this domain share a clock or will toggle in a predictable way. I.e., this domain can be used to describe asynchronous signals or static signals (like strap pins).
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- ClockDomain.scala
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Construct a type of this domain kind.
Construct a type of this domain kind.
For a given domain, this is used to create a Chisel type which can be used in a port. This is typically used to create domain type ports.
E.g., to create a chisel3.domains.ClockDomain port, use:
import chisel3.domains.ClockDomain val A = IO(Input(ClockDomain.Type()))
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A sequence of name--type pairs that define the schema for this domain.
A sequence of name--type pairs that define the schema for this domain.
The fields comprise the information that a user, after Verilog generation, should set in order to interact with, generate collateral files related to, or check the correctness of their choices for a domain.
Alternatively, the fields are the "parameters" for the domain. E.g., a clock domain could be parameterzied by an integer frequency. Chisel itself has no knowledge of this frequency, nor does it need a frequency to generate Verilog. However, in order to generate an implementation constraints file, the user must provide a frequency.
To change the fields from the default, override this method in your domain.
override def fields: Seq[(String, Field.Type)] = Seq( "foo" -> Field.Boolean )
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.