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Chisel Operators

Chisel defines a set of hardware operators:

Bitwise operatorsValid on: SInt, UInt, Bool
val invertedX = ~xBitwise NOT
val hiBits = x & "h_ffff_0000".UBitwise AND
val flagsOut = flagsIn | overflowBitwise OR
val flagsOut = flagsIn ^ toggleBitwise XOR
Bitwise reductions.Valid on: SInt and UInt. Returns Bool.
val allSet = x.andRAND reduction
val anySet = x.orROR reduction
val parity = x.xorRXOR reduction
Equality comparison.Valid on: SInt, UInt, and Bool. Returns Bool.
val equ = x === yEquality
val neq = x =/= yInequality
ShiftsValid on: SInt and UInt
val twoToTheX = 1.S << xLogical shift left
val hiBits = x >> 16.URight shift (logical on UInt and arithmetic on SInt).
Bitfield manipulationValid on: SInt, UInt, and Bool.
val xLSB = x(0)Extract single bit, LSB has index 0.
val xTopNibble = x(15, 12)Extract bit field from end to start bit position.
val usDebt = Fill(3, "hA".U)Replicate a bit string multiple times.
val float = Cat(sign, exponent, mantissa)Concatenates bit fields, with first argument on left.
Logical OperationsValid on: Bool
val sleep = !busyLogical NOT
val hit = tagMatch && validLogical AND
`val stall = src1busy
val out = Mux(sel, inTrue, inFalse)Two-input mux where sel is a Bool
Arithmetic operationsValid on Nums: SInt and UInt.
val sum = a + b or val sum = a +% bAddition (without width expansion)
val sum = a +& bAddition (with width expansion)
val diff = a - b or val diff = a -% bSubtraction (without width expansion)
val diff = a -& bSubtraction (with width expansion)
val prod = a * bMultiplication
val div = a / bDivision
val mod = a % bModulus
Arithmetic comparisonsValid on Nums: SInt and UInt. Returns Bool.
val gt = a > bGreater than
val gte = a >= bGreater than or equal
val lt = a < bLess than
val lte = a <= bLess than or equal

Our choice of operator names was constrained by the Scala language. We have to use triple equals=== for equality and =/= for inequality to allow the native Scala equals operator to remain usable.

The Chisel operator precedence is not directly defined as part of the Chisel language. Practically, it is determined by the evaluation order of the circuit, which naturally follows the Scala operator precedence. If in doubt of operator precedence, use parentheses.

The Chisel/Scala operator precedence is similar but not identical to precedence in Java or C. Verilog has the same operator precedence as C, but VHDL does not. Verilog has precedence ordering for logic operations, but in VHDL those operators have the same precedence and are evaluated from left to right.