Packages

  • package root
    Definition Classes
    root
  • package chisel3

    This package contains the main chisel3 API.

    This package contains the main chisel3 API.

    Definition Classes
    root
  • package testers

    The testers package provides the basic interface for chisel testers.

    The testers package provides the basic interface for chisel testers.

    Definition Classes
    chisel3
  • BasicTester
  • TesterDriver
c

chisel3.testers

BasicTester

class BasicTester extends Module

Source
BasicTester.scala
Type Hierarchy
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. BasicTester
  2. Module
  3. ImplicitReset
  4. ImplicitClock
  5. RawModule
  6. BaseModule
  7. IsInstantiable
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
Implicitly
  1. by BaseModuleExtensions
  2. by IsInstantiableExtensions
  3. by any2stringadd
  4. by StringFormat
  5. by Ensuring
  6. by ArrowAssoc
  1. Hide All
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new BasicTester()

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. def +(other: String): String
    Implicit
    This member is added by an implicit conversion from BasicTester toany2stringadd[BasicTester] performed by method any2stringadd in scala.Predef.
    Definition Classes
    any2stringadd
  4. def ->[B](y: B): (BasicTester, B)
    Implicit
    This member is added by an implicit conversion from BasicTester toArrowAssoc[BasicTester] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @inline()
  5. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  6. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T

    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef must be a chisel type and not be bound to hardware.

    Also registers an Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

    Attributes
    protected
    Definition Classes
    BaseModule
  8. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  9. def _moduleDefinitionIdentifierProposal: String
    Attributes
    protected
    Definition Classes
    BaseModule
  10. def _sourceInfo: SourceInfo
    Attributes
    protected
    Definition Classes
    BaseModule
  11. def _traitModuleDefinitionIdentifierProposal: Option[String]
    Attributes
    protected
    Definition Classes
    BaseModule
  12. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  13. def atModuleBodyEnd(gen: => Unit): Unit

    Hook to invoke hardware generators after the rest of the Module is constructed.

    Hook to invoke hardware generators after the rest of the Module is constructed.

    This is a power-user API, and should not normally be needed.

    In rare cases, it is necessary to run hardware generators at a late stage, but still within the scope of the Module. In these situations, atModuleBodyEnd may be used to register such generators. For example:

    class Example extends RawModule {
      atModuleBodyEnd {
        val extraPort0 = IO(Output(Bool()))
        extraPort0 := 0.B
      }
    }

    Any generators registered with atModuleBodyEnd are the last code to execute when the Module is constructed. The execution order is:

    • The constructors of any super classes or traits the Module extends
    • The constructor of the Module itself
    • The atModuleBodyEnd generators

    The atModuleBodyEnd generators execute in the lexical order they appear in the Module constructor.

    For example:

    trait Parent {
      // Executes first.
      val foo = ...
    }
    
    class Example extends Parent {
      // Executes second.
      val bar = ...
    
      atModuleBodyEnd {
        // Executes fourth.
        val qux = ...
      }
    
      atModuleBodyEnd {
        // Executes fifth.
        val quux = ...
      }
    
      // Executes third..
      val baz = ...
    }

    If atModuleBodyEnd is used in a Definition, any generated hardware will be included in the Definition. However, it is currently not possible to annotate any val within atModuleBodyEnd as @public.

    Attributes
    protected
    Definition Classes
    RawModule
  14. def circuitName: String
    Definition Classes
    HasId
  15. final val clock: Clock
    Definition Classes
    Module
  16. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native()
  17. final val definitionIdentifier: String

    Represents an eagerly-determined unique and descriptive identifier for this module

    Represents an eagerly-determined unique and descriptive identifier for this module

    Definition Classes
    BaseModule
  18. def desiredName: String

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The name of a module approximates the behavior of the Java Reflection getSimpleName method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:

    - Anonymous modules will get an "_Anon" tag - Modules defined in functions will use their class name and not a numeric name

    Definition Classes
    BaseModule
    Note

    If you want a custom or parametric name, override this method.

  19. def endIOCreation()(implicit si: SourceInfo): Unit

    Disallow any more IO creation for this module.

    Disallow any more IO creation for this module.

    Definition Classes
    BaseModule
  20. def ensuring(cond: (BasicTester) => Boolean, msg: => Any): BasicTester
    Implicit
    This member is added by an implicit conversion from BasicTester toEnsuring[BasicTester] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  21. def ensuring(cond: (BasicTester) => Boolean): BasicTester
    Implicit
    This member is added by an implicit conversion from BasicTester toEnsuring[BasicTester] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  22. def ensuring(cond: Boolean, msg: => Any): BasicTester
    Implicit
    This member is added by an implicit conversion from BasicTester toEnsuring[BasicTester] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  23. def ensuring(cond: Boolean): BasicTester
    Implicit
    This member is added by an implicit conversion from BasicTester toEnsuring[BasicTester] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  24. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  25. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  26. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable])
  27. def finish(): Unit

    The finish method provides a hook that subclasses of BasicTester can use to alter a circuit after their constructor has been called.

    The finish method provides a hook that subclasses of BasicTester can use to alter a circuit after their constructor has been called. For example, a specialized tester subclassing BasicTester could override finish in order to add flow control logic for a decoupled io port of a device under test

  28. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  29. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  30. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  31. def hasSeed: Boolean

    returns

    Whether either autoName or suggestName has been called

    Definition Classes
    HasId
  32. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  33. def implicitClock: Clock

    Method that should point to the user-defined Clock

    Method that should point to the user-defined Clock

    Attributes
    protected
    Definition Classes
    ModuleImplicitClock
  34. def implicitReset: Reset

    Method that should point to the user-defined Reset

    Method that should point to the user-defined Reset

    Attributes
    protected
    Definition Classes
    ModuleImplicitReset
  35. def instanceName: String

    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  36. val io: Bundle
  37. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  38. final lazy val name: String

    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  39. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  40. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  41. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  42. def parentModName: String
    Definition Classes
    HasId → InstanceId
  43. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  44. def pathName: String
    Definition Classes
    HasId → InstanceId
  45. def popCount(n: Long): Int
  46. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  47. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  48. final val reset: Reset
    Definition Classes
    Module
  49. def resetType: Type

    Override this to explicitly set the type of reset you want on this module , before any reset inference

    Override this to explicitly set the type of reset you want on this module , before any reset inference

    Definition Classes
    Module
  50. def stop()(implicit sourceInfo: SourceInfo): Unit

    Ends the test reporting success.

    Ends the test reporting success.

    Does not fire when in reset (defined as the encapsulating Module's reset). If your definition of reset is not the encapsulating Module's reset, you will need to gate this externally.

  51. def suggestName(seed: => String): BasicTester.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

    seed

    The seed for the name of this component

    returns

    this object

    Definition Classes
    HasId
  52. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  53. final def toAbsoluteTarget: IsModule

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  54. def toDefinition: Definition[BasicTester]
    Implicit
    This member is added by an implicit conversion from BasicTester toBaseModuleExtensions[BasicTester] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
    Definition Classes
    BaseModuleExtensions
  55. final def toNamed: ModuleName

    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  56. final def toRelativeTarget(root: Option[BaseModule]): IsModule

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    BaseModule
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The BaseModule must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  57. def toString(): String
    Definition Classes
    AnyRef → Any
  58. final def toTarget: ModuleTarget

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  59. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  60. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  61. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()

Shadowed Implicit Value Members

  1. def toInstance: Instance[BasicTester]
    Implicit
    This member is added by an implicit conversion from BasicTester toBaseModuleExtensions[BasicTester] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
    Shadowing
    This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
    To access this member you can use a type ascription:
    (basicTester: BaseModuleExtensions[BasicTester]).toInstance
    Definition Classes
    BaseModuleExtensions
  2. def toInstance: Instance[BasicTester]
    Implicit
    This member is added by an implicit conversion from BasicTester toIsInstantiableExtensions[BasicTester] performed by method IsInstantiableExtensions in chisel3.experimental.hierarchy.core.IsInstantiable.
    Shadowing
    This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
    To access this member you can use a type ascription:
    (basicTester: IsInstantiableExtensions[BasicTester]).toInstance
    Definition Classes
    IsInstantiableExtensions

Deprecated Value Members

  1. def formatted(fmtstr: String): String
    Implicit
    This member is added by an implicit conversion from BasicTester toStringFormat[BasicTester] performed by method StringFormat in scala.Predef.
    Definition Classes
    StringFormat
    Annotations
    @deprecated @inline()
    Deprecated

    (Since version 2.12.16) Use formatString.format(value) instead of value.formatted(formatString), or use the f"" string interpolator. In Java 15 and later, formatted resolves to the new method in String which has reversed parameters.

  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  6. def [B](y: B): (BasicTester, B)
    Implicit
    This member is added by an implicit conversion from BasicTester toArrowAssoc[BasicTester] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @deprecated
    Deprecated

    (Since version 2.13.0) Use -> instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.

Inherited from Module

Inherited from ImplicitReset

Inherited from ImplicitClock

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Inherited by implicit conversion BaseModuleExtensions fromBasicTester to BaseModuleExtensions[BasicTester]

Inherited by implicit conversion IsInstantiableExtensions fromBasicTester to IsInstantiableExtensions[BasicTester]

Inherited by implicit conversion any2stringadd fromBasicTester to any2stringadd[BasicTester]

Inherited by implicit conversion StringFormat fromBasicTester to StringFormat[BasicTester]

Inherited by implicit conversion Ensuring fromBasicTester to Ensuring[BasicTester]

Inherited by implicit conversion ArrowAssoc fromBasicTester to ArrowAssoc[BasicTester]

Ungrouped