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Chisel Users Community

If you're a Chisel user and want to stay connected to the wider user community, any of the following are great avenues:

Projects Using Chisel/FIRRTL

If you want to add your project to the list, let us know on the Chisel users mailing list!


Rocket Chip GeneratorRISC-V System-on-Chip Generator, 5-stage RISC-V Microprocessor@ucb-bar, @sifiveReport
Berkeley Out-of-order MachineRISC-V Out-of-order/Multi-issue Microprocessor@ucb-barSite, Thesis
RISC-V Mini3-stage RISC-V Microprocessor@ucb-bar
Sodor Processor CollectionEducational RISC-V Microprocessors (1, 2, 3, 5-stage)@ucb-bar
PatmosTime-predictable VLIW processor@t-crestSite
OpenSoC FabricParametrizable Network-on-Chip Generator@LBL-CoDExSite
HwachaDecoupled Vector-fetch Accelerator@ucb-barReport
DANAMultilayer Perceptron Accelerator for Rocket@bu-icsgPaper
GemminiSystolic-array Accelerator Generator@ucb-barPaper
Edge TPUAI Inference Accelerator@googleVideo
ChiselFlowInformation Flow Types in Chisel3@apl-cornellPaper
PHMonProgrammable Hardware Monitor@bu-icsgPaper
DINO CPUDavis In-Order (DINO) CPU models@jlpteachingPaper
QuasarCHISEL implementation of SweRV-EL2@Lampro-MellonVideo
FP Divider Pipelined / Not PipelinedIEEE binary 32-bit divider using Harmonized Parabolic Synthesis@SsavasPaper
Square Root Pipelined / Not PipelinedSquare Root using Harmonized Parabolic Synthesis@SsavasPaper
PillarsA Consistent CGRA Design Framework@pku-dasysPaper, Video
TensilMachine Learning Accelerators@tensil-aiWebsite
TwineA Chisel Extension for Component-Level Heterogeneous Design@shibo-chenPaper
RISCVAssemblerA RISC-V assembler library for Scala/Chisel projects@carlosedpSite, Demo Site)
SoC-NowA plug and play supported RISC-V System-on-Chip Generator, 5-stage RISC-V Microprocessor@merleduSite, Poster, Video


Tywaves (demo)Type-based waveform viewer for Chisel@rameloniChisel backend, Surfer-Tywaves fork


MIDAS/DESSERT/Golden GateFPGA Accelerated Simulation@ucb-barPapers 1, 2, 3, Video
ChiffreRun-time Fault Injection@IBMPaper
SIRRTLSecurity-typed FIRRTL@apl-cornellPaper
obfuscationTransforms to Obfuscate FIRRTL Circuits@jpsety
Area/Timing EstimatesTransforms for Area and Timing Estimates@intelVideo

Chisel Developers Community

If you want to get more involved with the Chisel/FIRRTL ecosystem of projects, feel free to reach out to us on any of the mediums above. If you prefer to dive right in (or have bugs to report), a complete list of the associated Chisel/FIRRTL ecosystem of projects is below:


Chisel, FIRRTL, and all related projects would not be possible without the contributions of our fantastic developer community. The following people have contributed to the current release of the projects:


While Chisel has come a long way since 2012, the original Chisel paper provides some background on motivations and an overview of the (now deprecated) Chisel 2 language:

The FIRRTL IR and FIRRTL compiler, introduced as part of Chisel 3, are discussed in both the following paper and specification1:

Finally, Chisel's functional programming and bit-width inference ideas were inspired by earlier work on a hardware description language called Gel:


If you use Chisel in your research, consider citing:

author={J. {Bachrach} and H. {Vo} and B. {Richards} and Y. {Lee} and A. {Waterman} and R {Avižienis} and J. {Wawrzynek} and K. {Asanović}},
booktitle={DAC Design Automation Conference 2012},
title={Chisel: Constructing hardware in a Scala embedded language},
keywords={application specific integrated circuits;C++ language;field programmable gate arrays;hardware description languages;Chisel;Scala embedded language;hardware construction language;hardware design abstraction;functional programming;type inference;high-speed C++-based cycle-accurate software simulator;low-level Verilog;FPGA;standard ASIC flow;Hardware;Hardware design languages;Generators;Registers;Wires;Vectors;Finite impulse response filter;CAD},

If you use FIRRTL in your research consider citing:

author={A. Izraelevitz and J. Koenig and P. Li and R. Lin and A. Wang and A. Magyar and D. Kim and C. Schmidt and C. Markley and J. Lawson and J. Bachrach},
booktitle={2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
title={Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks,
and transformations},
keywords={field programmable gate arrays;hardware description languages;program compilers;software reusability;hardware development practices;hardware libraries;open-source hardware intermediate representation;hardware compiler transformations;Hardware construction languages;retargetable compilers;software development;virtual Cambrian explosion;hardware compiler frameworks;parameterized libraries;FIRRTL;FPGA mappings;Chisel;Flexible Intermediate Representation for RTL;Reusability;Hardware;Libraries;Hardware design languages;Field programmable gate arrays;Tools;Open source software;RTL;Design;FPGA;ASIC;Hardware;Modeling;Reusability;Hardware Design Language;Hardware Construction Language;Intermediate Representation;Compiler;Transformations;Chisel;FIRRTL},
Author = {Li, Patrick S. and Izraelevitz, Adam M. and Bachrach, Jonathan},
Title = {Specification for the FIRRTL Language},
Institution = {EECS Department, University of California, Berkeley},
Year = {2016},
Month = {Feb},
URL = {},
Number = {UCB/EECS-2016-9}


  1. This specification is provided for historical perspective. For the latest version of the FIRRTL specification you can use this link.